def main():
INFO = "RTL Converter with Pyverilog"
VERSION = ipgen.utils.version.VERSION
USAGE = "Usage: python rtlconverter.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="userlogic",help="Top module, Default=userlogic")
optparser.add_option("-o","--output",dest="outputfile",
default="out.v",help="Output file name, Default=out.v")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
converter = RtlConverter(filelist, options.topmodule,
include=options.include,
define=options.define)
ast = converter.generate()
(master_dict, slave_dict) = converter.getResourceDefinitions()
converter.dumpTargetObject()
converter.dumpResourceDefinitions()
asttocode = ASTCodeGenerator()
code = asttocode.visit(ast)
f = open(options.outputfile, 'w')
f.write(code)
f.close()
def main():
INFO = "RTL Converter with Pyverilog"
VERSION = ipgen.utils.version.VERSION
USAGE = "Usage: python rtlconverter.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="userlogic",
help="Top module, Default=userlogic")
optparser.add_option("-o",
"--output",
dest="outputfile",
default="out.v",
help="Output file name, Default=out.v")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
converter = RtlConverter(filelist,
options.topmodule,
include=options.include,
define=options.define)
ast = converter.generate()
(master_dict, slave_dict) = converter.getResourceDefinitions()
converter.dumpTargetObject()
converter.dumpResourceDefinitions()
asttocode = ASTCodeGenerator()
code = asttocode.visit(ast)
f = open(options.outputfile, 'w')
f.write(code)
f.close()
def build(self,
configs,
userlogic_topmodule,
userlogic_filelist,
include=None,
define=None,
memimg=None,
usertest=None,
skip_not_found=False,
ignore_protocol_error=False):
# default values
ext_burstlength = 256
if configs['single_clock'] and (configs['hperiod_ulogic'] !=
configs['hperiod_bus']):
raise ValueError(
"All clock periods should be same in single clock mode.")
# User RTL Conversion
converter = RtlConverter(userlogic_filelist,
userlogic_topmodule,
include=include,
define=define)
userlogic_ast = converter.generate(skip_not_found)
(masterlist, slavelist) = converter.getResourceDefinitions()
top_parameters = converter.getTopParameters()
top_ioports = converter.getTopIOPorts()
not_found_modules = converter.getNotFoundModules()
# dump
converter.dumpTargetObject()
# Code Generator
asttocode = ASTCodeGenerator()
userlogic_code = asttocode.visit(userlogic_ast)
asttocode = ASTCodeGenerator()
def_top_parameters = []
def_top_localparams = []
def_top_ioports = []
name_top_ioports = []
for p in top_parameters.values():
r = asttocode.visit(p)
if r.count('localparam'):
def_top_localparams.append(r)
else:
def_top_parameters.append(r.replace(';', ','))
for pk, (pv, pwidth) in top_ioports.items():
if configs['if_type'] == 'avalon':
new_pv = copy.deepcopy(pv)
new_pv.name = 'coe_' + new_pv.name
new_pv = vast.Ioport(
new_pv, vast.Wire(new_pv.name, new_pv.width,
new_pv.signed))
def_top_ioports.append(asttocode.visit(new_pv))
else:
new_pv = vast.Ioport(pv, vast.Wire(pv.name, pv.width,
pv.signed))
def_top_ioports.append(asttocode.visit(new_pv))
name_top_ioports.append(pk)
node_template_file = (
'node_axi.txt' if configs['if_type'] == 'axi' else
'node_avalon.txt' if configs['if_type'] == 'avalon' else
#'node_wishborn.txt' if configs['if_type'] == 'wishborn' else
'node_general.txt')
node_code = self.render(node_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'])
# finalize of code generation
synthesized_code_list = []
synthesized_code_list.append(node_code)
synthesized_code_list.append(userlogic_code)
common_code_list = []
if configs['if_type'] == 'axi':
common_code_list.append(
open(TEMPLATE_DIR + 'axi_master_interface.v', 'r').read())
common_code_list.append(
open(TEMPLATE_DIR + 'axi_lite_master_interface.v', 'r').read())
common_code_list.append(
open(TEMPLATE_DIR + 'axi_slave_interface.v', 'r').read())
common_code_list.append(
open(TEMPLATE_DIR + 'axi_lite_slave_interface.v', 'r').read())
if configs['if_type'] == 'avalon':
common_code_list.append(
open(TEMPLATE_DIR + 'avalon_master_interface.v', 'r').read())
common_code_list.append(
open(TEMPLATE_DIR + 'avalon_lite_master_interface.v',
'r').read())
common_code_list.append(
open(TEMPLATE_DIR + 'avalon_slave_interface.v', 'r').read())
common_code_list.append(
open(TEMPLATE_DIR + 'avalon_lite_slave_interface.v',
'r').read())
synthesized_code = ''.join(synthesized_code_list)
common_code = ''.join(common_code_list)
# Print settings
print("----------------------------------------")
print("Synthesis Setting")
for k, v in sorted(configs.items(), key=lambda x: x[0]):
print(" %s : %s" % (str(k), str(v)))
# write to file, without AXI interfaces
if configs['if_type'] == 'general':
self.build_package_general(configs, synthesized_code, common_code)
return
if configs['if_type'] == 'axi':
self.build_package_axi(configs, synthesized_code, common_code,
masterlist, slavelist, top_parameters,
top_ioports, userlogic_topmodule, memimg,
usertest, ignore_protocol_error)
return
if configs['if_type'] == 'avalon':
self.build_package_avalon(configs, synthesized_code, common_code,
masterlist, slavelist, top_parameters,
top_ioports, userlogic_topmodule, memimg,
usertest, ignore_protocol_error)
return
raise ValueError("Interface type '%s' is not supported." %
configs['if_type'])
def build(
self,
configs,
userlogic_topmodule,
userlogic_filelist,
include=None,
define=None,
memimg=None,
usertest=None,
skip_not_found=False,
ignore_protocol_error=False,
):
# default values
ext_burstlength = 256
if configs["single_clock"] and (configs["hperiod_ulogic"] != configs["hperiod_bus"]):
raise ValueError("All clock periods should be same in single clock mode.")
# User RTL Conversion
converter = RtlConverter(userlogic_filelist, userlogic_topmodule, include=include, define=define)
userlogic_ast = converter.generate(skip_not_found)
(masterlist, slavelist) = converter.getResourceDefinitions()
top_parameters = converter.getTopParameters()
top_ioports = converter.getTopIOPorts()
not_found_modules = converter.getNotFoundModules()
# dump
converter.dumpTargetObject()
# Code Generator
asttocode = ASTCodeGenerator()
userlogic_code = asttocode.visit(userlogic_ast)
asttocode = ASTCodeGenerator()
def_top_parameters = []
def_top_localparams = []
def_top_ioports = []
name_top_ioports = []
for p in top_parameters.values():
r = asttocode.visit(p)
if r.count("localparam"):
def_top_localparams.append(r)
else:
def_top_parameters.append(r.replace(";", ","))
for pk, (pv, pwidth) in top_ioports.items():
if configs["if_type"] == "avalon":
new_pv = copy.deepcopy(pv)
new_pv.name = "coe_" + new_pv.name
new_pv = vast.Ioport(new_pv, vast.Wire(new_pv.name, new_pv.width, new_pv.signed))
def_top_ioports.append(asttocode.visit(new_pv))
else:
new_pv = vast.Ioport(pv, vast.Wire(pv.name, pv.width, pv.signed))
def_top_ioports.append(asttocode.visit(new_pv))
name_top_ioports.append(pk)
node_template_file = (
"node_axi.txt"
if configs["if_type"] == "axi"
else "node_avalon.txt"
if configs["if_type"] == "avalon"
else
#'node_wishborn.txt' if configs['if_type'] == 'wishborn' else
"node_general.txt"
)
node_code = self.render(
node_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs["ext_addrwidth"],
ext_burstlength=ext_burstlength,
single_clock=configs["single_clock"],
)
# finalize of code generation
synthesized_code_list = []
synthesized_code_list.append(node_code)
synthesized_code_list.append(userlogic_code)
common_code_list = []
if configs["if_type"] == "axi":
common_code_list.append(open(TEMPLATE_DIR + "axi_master_interface.v", "r").read())
common_code_list.append(open(TEMPLATE_DIR + "axi_lite_master_interface.v", "r").read())
common_code_list.append(open(TEMPLATE_DIR + "axi_slave_interface.v", "r").read())
common_code_list.append(open(TEMPLATE_DIR + "axi_lite_slave_interface.v", "r").read())
if configs["if_type"] == "avalon":
common_code_list.append(open(TEMPLATE_DIR + "avalon_master_interface.v", "r").read())
common_code_list.append(open(TEMPLATE_DIR + "avalon_lite_master_interface.v", "r").read())
common_code_list.append(open(TEMPLATE_DIR + "avalon_slave_interface.v", "r").read())
common_code_list.append(open(TEMPLATE_DIR + "avalon_lite_slave_interface.v", "r").read())
synthesized_code = "".join(synthesized_code_list)
common_code = "".join(common_code_list)
# Print settings
print("----------------------------------------")
print("Synthesis Setting")
for k, v in sorted(configs.items(), key=lambda x: x[0]):
print(" %s : %s" % (str(k), str(v)))
# write to file, without AXI interfaces
if configs["if_type"] == "general":
self.build_package_general(configs, synthesized_code, common_code)
return
if configs["if_type"] == "axi":
self.build_package_axi(
configs,
synthesized_code,
common_code,
masterlist,
slavelist,
top_parameters,
top_ioports,
userlogic_topmodule,
memimg,
usertest,
ignore_protocol_error,
)
return
if configs["if_type"] == "avalon":
self.build_package_avalon(
configs,
synthesized_code,
common_code,
masterlist,
slavelist,
top_parameters,
top_ioports,
userlogic_topmodule,
memimg,
usertest,
ignore_protocol_error,
)
return
raise ValueError("Interface type '%s' is not supported." % configs["if_type"])