def convert():
input_interface = RGB()
output_interface = outputs_frontend_new()
clock = Signal(bool(0))
reset = ResetSignal(0, active=True, async=False)
inst = frontend_top_level_v2(input_interface, output_interface, clock, reset)
inst.convert(hdl='vhdl')
inst.convert(hdl='verilog')
def convert():
input_interface = RGB()
output_interface = outputs_frontend_new()
clock = Signal(bool(0))
reset = ResetSignal(0, active=True, async=False)
inst = frontend_top_level_v2(input_interface, output_interface, clock,
reset)
inst.convert(hdl='vhdl')
inst.convert(hdl='verilog')
def test_frontend():
"""Frontend Part of the JPEG Encoder MyHDL Test
In this test is verified the correct behavior of the frontend part
of the endocer
"""
samples, N = 2, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = inputs_frontend_new()
outputs = outputs_frontend_new()
in_out_data = InputsAndOutputs(samples, N)
in_out_data.initialize()
@block
def bench_frontend():
tdut = frontend_top_level_v2(inputs, outputs, clock, reset)
tbclock = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for n in range(3):
for j in range(N):
for k in range(N):
inputs.red.next = in_out_data.inputs[i][0][j][k]
inputs.green.next = in_out_data.inputs[i][1][j][k]
inputs.blue.next = in_out_data.inputs[i][2][j][k]
yield clock.posedge
@instance
def monitor():
samples_count = 0
outputs_count = 0
outputs_list = []
clock_cycle_counter = 0
while(outputs.data_valid == False):
yield clock.posedge
clock_cycle_counter += 1
while samples_count != samples:
print("Processing Block %d" %(samples_count+1))
for i in range(3):
while(outputs_count != 64):
outputs_list.append(int(outputs.data_out))
outputs_count += 1
clock_cycle_counter += 1
yield clock.posedge
out_print(in_out_data.outputs[samples_count],
outputs_list, N, i)
outputs_count = 0
outputs_list = []
samples_count += 1
print("Clock Cycles taken for the block conversion:",
clock_cycle_counter)
raise StopSimulation
return tdut, tbclock, tbstim, monitor
run_testbench(bench_frontend)
def test_frontend_conversion():
"""Convertible Frontend Part of the JPEG Encoder Test
This is the convertible testbench which ensures that the overall
design is convertible and verified for its correct behavior"""
samples, N = 2, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = inputs_frontend_new()
outputs = outputs_frontend_new()
in_out_data = InputsAndOutputs(samples, N)
in_out_data.initialize()
r_rom, g_rom, b_rom, y_out_rom,\
cb_out_rom, cr_out_rom = in_out_data.get_rom_tables()
@block
def bench_frontend():
print_sig = Signal(intbv(0, min=-outputs.out_range, max=outputs.out_range))
tdut = frontend_top_level_v2(inputs, outputs, clock, reset)
tbclock = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
@instance
def tbstim():
yield reset.negedge
inputs.data_valid.next = True
for i in range(samples):
for n in range(3):
for j in range(64 * i, 64 * (i + 1)):
inputs.red.next = r_rom[j]
inputs.green.next = g_rom[j]
inputs.blue.next = b_rom[j]
yield clock.posedge
@instance
def monitor():
samples_count = 0
outputs_count = 0
clock_cycle_counter = 0
yield outputs.data_valid.posedge
while(samples_count < samples):
print("Processing Block %d" % (samples_count))
for i in range(3):
while(outputs_count != 64):
if i == 0:
print_sig.next = y_out_rom[outputs_count + samples_count*64]
elif i == 1:
print_sig.next = cb_out_rom[outputs_count + samples_count*64]
else:
print_sig.next = cr_out_rom[outputs_count + samples_count*64]
yield delay(1)
print("%d %d" % (outputs.data_out, print_sig))
outputs_count += 1
clock_cycle_counter += 1
yield clock.posedge
outputs_count = 0
samples_count += 1
raise StopSimulation
return tdut, tbclock, tbstim, monitor, tbrst
assert bench_frontend().verify_convert() == 0