def generate_pond_api(self, ctrl_rd, ctrl_wr, num_acc=1):
tform_ranges_rd = [0] * num_acc
tform_strides_rd = [0] * num_acc
tform_ranges_rd_sched = [0] * num_acc
tform_strides_rd_sched = [0] * num_acc
tform_ranges_wr = [0] * num_acc
tform_strides_wr = [0] * num_acc
tform_ranges_wr_sched = [0] * num_acc
tform_strides_wr_sched = [0] * num_acc
dim_rd = [0] * num_acc
dim_wr = [0] * num_acc
for i in range(num_acc):
(tform_ranges_rd[i],
tform_strides_rd[i]) = transform_strides_and_ranges(
ctrl_rd[i][0], ctrl_rd[i][1], ctrl_rd[i][2])
(tform_ranges_wr[i],
tform_strides_wr[i]) = transform_strides_and_ranges(
ctrl_wr[i][0], ctrl_wr[i][1], ctrl_wr[i][2])
(tform_ranges_rd_sched[i],
tform_strides_rd_sched[i]) = transform_strides_and_ranges(
ctrl_rd[i][0], ctrl_rd[i][5], ctrl_rd[i][2])
(tform_ranges_wr_sched[i],
tform_strides_wr_sched[i]) = transform_strides_and_ranges(
ctrl_wr[i][0], ctrl_wr[i][5], ctrl_wr[i][2])
dim_rd[i] = ctrl_rd[i][2]
dim_wr[i] = ctrl_wr[i][2]
new_config = {}
for i in range(num_acc):
new_config[f"rf_read_iter_{i}_dimensionality"] = ctrl_rd[i][2]
new_config[f"rf_read_addr_{i}_starting_addr"] = ctrl_rd[i][3]
new_config[
f"rf_read_sched_{i}_sched_addr_gen_starting_addr"] = ctrl_rd[
i][4]
new_config[f"rf_read_sched_{i}_enable"] = 1
for j in range(dim_rd[i]):
new_config[f"rf_read_addr_{i}_strides_{j}"] = tform_strides_rd[
i][j]
new_config[f"rf_read_iter_{i}_ranges_{j}"] = tform_ranges_rd[
i][j]
new_config[
f"rf_read_sched_{i}_sched_addr_gen_strides_{j}"] = tform_strides_rd_sched[
i][j]
new_config[f"rf_write_iter_{i}_dimensionality"] = ctrl_wr[i][2]
new_config[f"rf_write_addr_{i}_starting_addr"] = ctrl_wr[i][3]
new_config[
f"rf_write_sched_{i}_sched_addr_gen_starting_addr"] = ctrl_wr[
i][4]
new_config[f"rf_write_sched_{i}_enable"] = 1
for j in range(dim_wr[i]):
new_config[
f"rf_write_addr_{i}_strides_{j}"] = tform_strides_wr[i][j]
new_config[f"rf_write_iter_{i}_ranges_{j}"] = tform_ranges_wr[
i][j]
new_config[
f"rf_write_sched_{i}_sched_addr_gen_strides_{j}"] = tform_strides_wr_sched[
i][j]
return new_config
def test_addr_design(test_rand,
design,
starting_addr=0,
strides_0=15,
strides_1=13,
ranges_0=5,
ranges_1=6):
if test_rand:
max_value = 2**5
starting_addr = random.randint(0, max_value - 1)
strides_0 = random.randint(0, max_value - 1)
strides_1 = random.randint(0, max_value - 1)
ranges_0 = random.randint(0, max_value - 1)
ranges_1 = random.randint(0, max_value - 1)
print(starting_addr, strides_0, strides_1, ranges_0, ranges_1)
# set up addressor model
model_ag = AddrGenModel(2, 16)
config = {}
config["starting_addr"] = starting_addr
config["dimensionality"] = 2
config["strides_0"] = strides_0
config["strides_1"] = strides_1
config["ranges_0"] = ranges_0
config["ranges_1"] = ranges_1
model_ag.set_config(config)
# set up frail design with Verilog
frail_dir = pathlib.Path(__file__).parent.parent.absolute()
# get Magma circuit from Verilog
dut = m.define_from_verilog_file(f"{frail_dir}/verilog/{design}.v",
target_modules=[design],
type_map={"clk": m.In(m.Clock)})[0]
print(f"Imported as magma circuit: {dut}")
tester = fault.Tester(dut, dut.clk)
# no need to rst_n or clk_en yet
# config regs
if design in ("design_b", "op_design", "nested"):
tranges, tstrides = transform_strides_and_ranges(
[ranges_0, ranges_1], [strides_0, strides_1], 2)
tester.circuit.x_max = ranges_0 #tranges[0]
tester.circuit.x_stride = tstrides[0]
tester.circuit.y_max = ranges_1 #tranges[1]
tester.circuit.y_stride = tstrides[1]
# tester.circuit.config_68_74_op = tstrides[1]
# tester.circuit.config_125_131_op = tstrides[1]
tester.circuit.y_stride_op = tstrides[1]
tester.circuit.offset = starting_addr
# print("transformed:", tranges, tstrides)
elif design == "piecewise_addr_design":
tester.circuit.x_max = ranges_0
tester.circuit.x_stride_0 = strides_0
tester.circuit.x_stride_1 = strides_0
tester.circuit.y_max = ranges_1
tester.circuit.y_stride_0 = strides_1
tester.circuit.y_stride_1 = strides_1
tester.circuit.offset_0 = starting_addr
tester.circuit.offset_1 = starting_addr
tester.circuit.offset_2 = starting_addr
tester.circuit.offset_3 = starting_addr
tester.circuit.i0_piece = ranges_0
tester.circuit.i1_piece = ranges_1
else:
tester.circuit.x_max = ranges_0
tester.circuit.x_stride = strides_0
tester.circuit.y_max = ranges_1
tester.circuit.y_stride = strides_1
tester.circuit.offset = starting_addr
tester.circuit.step = 1
for i in range(min(1000, ranges_0 * ranges_1 - 1)):
# start with first addr on rising clk edge
tester.circuit.clk = 1
tester.step(2)
tester.eval()
model_ag.step()
tester.circuit.addr_out.expect(model_ag.get_address())
# print(model_ag.get_address())
with tempfile.TemporaryDirectory() as tempdir:
# tempdir = design
shutil.copy(f"{frail_dir}/verilog/{design}.v", tempdir)
tester.compile_and_run(target="verilator",
directory=tempdir,
skip_compile=True,
flags=["-Wno-fatal"])
def generate_pond_api(interconnect, pondcore, ctrl_rd, ctrl_wr, pe_x, pe_y,
config_data):
flattened = create_wrapper_flatten(pondcore.dut.internal_generator.clone(),
pondcore.dut.name)
(tform_ranges_rd,
tform_strides_rd) = transform_strides_and_ranges(ctrl_rd[0], ctrl_rd[1],
ctrl_rd[2])
(tform_ranges_wr,
tform_strides_wr) = transform_strides_and_ranges(ctrl_wr[0], ctrl_wr[1],
ctrl_wr[2])
name_out, val_out = trim_config(flattened, "tile_en", 1)
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_read_iter_0_dimensionality",
ctrl_rd[2])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_read_addr_0_starting_addr",
ctrl_rd[3])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_read_addr_0_strides_0",
tform_strides_rd[0])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_read_addr_0_strides_1",
tform_strides_rd[1])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_read_iter_0_ranges_0",
tform_ranges_rd[0])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_read_iter_0_ranges_1",
tform_ranges_rd[1])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(
flattened, "rf_read_sched_0_sched_addr_gen_starting_addr", ctrl_rd[4])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(
flattened, "rf_read_sched_0_sched_addr_gen_strides_0",
tform_strides_rd[0])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(
flattened, "rf_read_sched_0_sched_addr_gen_strides_1",
tform_strides_rd[1])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened,
"rf_write_iter_0_dimensionality",
ctrl_wr[2])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_write_addr_0_starting_addr",
ctrl_wr[3])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_write_addr_0_strides_0",
tform_strides_wr[0])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_write_addr_0_strides_1",
tform_strides_wr[1])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_write_iter_0_ranges_0",
tform_ranges_wr[0])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(flattened, "rf_write_iter_0_ranges_1",
tform_ranges_wr[1])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(
flattened, "rf_write_sched_0_sched_addr_gen_starting_addr", ctrl_wr[4])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(
flattened, "rf_write_sched_0_sched_addr_gen_strides_0",
tform_strides_wr[0])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
name_out, val_out = trim_config(
flattened, "rf_write_sched_0_sched_addr_gen_strides_1",
tform_strides_wr[1])
idx, value = pondcore.get_config_data(name_out, val_out)
config_data.append((interconnect.get_config_addr(idx, 1, pe_x,
pe_y), value))
def test_sram_formal():
sram_dut = SRAMFormal(
data_width=16, # CGRA Params
mem_width=64,
mem_depth=512,
banks=1,
input_addr_iterator_support=6,
output_addr_iterator_support=6,
input_sched_iterator_support=6,
output_sched_iterator_support=6,
config_width=16,
# output_config_width=16,
interconnect_input_ports=1, # Connection to int
interconnect_output_ports=1,
mem_input_ports=1,
mem_output_ports=1,
read_delay=1, # Cycle delay in read (SRAM vs Register File)
rw_same_cycle=False, # Does the memory allow r+w in same cycle?
agg_height=4)
lift_config_reg(sram_dut.internal_generator)
magma_dut = k.util.to_magma(sram_dut,
flatten_array=True,
check_flip_flop_always_ff=False)
tester = fault.Tester(magma_dut, magma_dut.clk)
in_ranges = [2, 8, 1]
in_addr_strides = [1, 2, 0]
in_addr_strt = 0
in_sched_strides = [4, 8, 0]
in_sched_strt = 4
dim = 3
(write_ranges,
tform_in_addr) = transform_strides_and_ranges(ranges=in_ranges,
strides=in_addr_strides,
dimensionality=dim)
(write_ranges,
tform_in_sched) = transform_strides_and_ranges(ranges=in_ranges,
strides=in_sched_strides,
dimensionality=dim)
out_ranges = [2, 8, 1]
out_addr_strides = [1, 2, 0]
out_addr_strt = 0
out_sched_strides = [4, 8, 0]
out_sched_strt = 6
dim = 3
(read_ranges,
tform_out_addr) = transform_strides_and_ranges(ranges=out_ranges,
strides=out_addr_strides,
dimensionality=dim)
(read_ranges,
tform_out_sched) = transform_strides_and_ranges(ranges=out_ranges,
strides=out_sched_strides,
dimensionality=dim)
config = {}
# config["sram_write_loops_ranges_0"] = 485
# config["sram_write_loops_ranges_1"] = 0
# config["sram_write_loops_ranges_2"] = 0
# config["sram_write_loops_ranges_3"] = 0
# config["sram_write_loops_ranges_4"] = 0
# config["sram_write_loops_ranges_5"] = 0
# # config["sram_read_sched_gen_sched_addr_gen_starting_addr"] = 5
# # config["sram_read_sched_gen_sched_addr_gen_strides_0"] = 3
# # config["sram_read_sched_gen_sched_addr_gen_strides_1"] = 1
# # config["sram_read_sched_gen_sched_addr_gen_strides_2"] = 65535
# # config["sram_read_sched_gen_sched_addr_gen_strides_3"] = 65535
# # config["sram_read_sched_gen_sched_addr_gen_strides_4"] = 65535
# # config["sram_read_sched_gen_sched_addr_gen_strides_5"] = 65535
# config["sram_write_addr_gen_strides_0"] = 65534
# config["sram_write_addr_gen_strides_1"] = 0
# config["sram_write_addr_gen_strides_2"] = 0
# config["sram_write_addr_gen_strides_3"] = 0
# config["sram_write_addr_gen_strides_4"] = 0
# config["sram_write_addr_gen_strides_5"] = 0
# config["sram_write_addr_gen_starting_addr"] = 33791
# config["sram_write_sched_gen_sched_addr_gen_starting_addr"] = 4
# config["sram_read_addr_gen_strides_0"] = 65535
# config["sram_read_addr_gen_strides_1"] = 65535
# config["sram_read_addr_gen_strides_2"] = 65535
# config["sram_read_addr_gen_strides_3"] = 65535
# config["sram_read_addr_gen_strides_4"] = 65535
# config["sram_read_addr_gen_strides_5"] = 65535
# config["sram_write_loops_dimensionality"] = 0
# # config["sram_read_loops_dimensionality"] = 0
# # config["sram_read_loops_ranges_0"] = 0
# # config["sram_read_loops_ranges_1"] = 65535
# # config["sram_read_loops_ranges_2"] = 65535
# # config["sram_read_loops_ranges_3"] = 65535
# # config["sram_read_loops_ranges_4"] = 65535
# # config["sram_read_loops_ranges_5"] = 65535
# config["sram_read_addr_gen_starting_addr"] = 511
# config["sram_write_sched_gen_sched_addr_gen_strides_0"] = 4
# config["sram_write_sched_gen_sched_addr_gen_strides_1"] = 0
# config["sram_write_sched_gen_sched_addr_gen_strides_2"] = 0
# config["sram_write_sched_gen_sched_addr_gen_strides_3"] = 0
# config["sram_write_sched_gen_sched_addr_gen_strides_4"] = 0
# config["sram_write_sched_gen_sched_addr_gen_strides_5"] = 0
# config["sram_read_loops_dimensionality"] = 0
# config["sram_read_sched_gen_sched_addr_gen_strides_0"] = 4
# config["sram_read_sched_gen_sched_addr_gen_strides_1"] = 65535
# config["sram_read_sched_gen_sched_addr_gen_strides_2"] = 65535
# config["sram_read_sched_gen_sched_addr_gen_strides_3"] = 65535
# config["sram_read_sched_gen_sched_addr_gen_strides_4"] = 65535
# config["sram_read_sched_gen_sched_addr_gen_strides_5"] = 65535
# config["sram_read_sched_gen_sched_addr_gen_starting_addr"] = 5
# config["sram_read_loops_ranges_0"] = 398
# config["sram_read_loops_ranges_1"] = 65535
# config["sram_read_loops_ranges_2"] = 65535
# config["sram_read_loops_ranges_3"] = 65535
# config["sram_read_loops_ranges_4"] = 65535
# config["sram_read_loops_ranges_5"] = 65535
config["sram_read_sched_gen_sched_addr_gen_starting_addr"] = 5
config["sram_write_loops_ranges_0"] = 65535
config["sram_write_loops_ranges_1"] = 65535
config["sram_write_loops_ranges_2"] = 65535
config["sram_write_loops_ranges_3"] = 65535
config["sram_write_loops_ranges_4"] = 65535
config["sram_write_loops_ranges_5"] = 65535
config["sram_read_sched_gen_sched_addr_gen_strides_0"] = 4
config["sram_read_sched_gen_sched_addr_gen_strides_1"] = 65535
config["sram_read_sched_gen_sched_addr_gen_strides_2"] = 65535
config["sram_read_sched_gen_sched_addr_gen_strides_3"] = 65535
config["sram_read_sched_gen_sched_addr_gen_strides_4"] = 65535
config["sram_read_sched_gen_sched_addr_gen_strides_5"] = 65535
config["sram_write_addr_gen_strides_0"] = 65535
config["sram_write_addr_gen_strides_1"] = 65535
config["sram_write_addr_gen_strides_2"] = 65535
config["sram_write_addr_gen_strides_3"] = 65535
config["sram_write_addr_gen_strides_4"] = 65535
config["sram_write_addr_gen_strides_5"] = 65535
config["sram_write_addr_gen_starting_addr"] = 65535
config["sram_write_sched_gen_sched_addr_gen_starting_addr"] = 4
config["sram_read_addr_gen_strides_0"] = 65535
config["sram_read_addr_gen_strides_1"] = 65535
config["sram_read_addr_gen_strides_2"] = 65535
config["sram_read_addr_gen_strides_3"] = 65535
config["sram_read_addr_gen_strides_4"] = 65535
config["sram_read_addr_gen_strides_5"] = 65535
config["sram_write_loops_dimensionality"] = 0
config["sram_read_loops_dimensionality"] = 0
config["sram_read_loops_ranges_0"] = 398
config["sram_read_loops_ranges_1"] = 65535
config["sram_read_loops_ranges_2"] = 65535
config["sram_read_loops_ranges_3"] = 65535
config["sram_read_loops_ranges_4"] = 65535
config["sram_read_loops_ranges_5"] = 65535
config["sram_read_addr_gen_starting_addr"] = 65535
config["sram_write_sched_gen_sched_addr_gen_strides_0"] = 4
config["sram_write_sched_gen_sched_addr_gen_strides_1"] = 65535
config["sram_write_sched_gen_sched_addr_gen_strides_2"] = 65535
config["sram_write_sched_gen_sched_addr_gen_strides_3"] = 65535
config["sram_write_sched_gen_sched_addr_gen_strides_4"] = 65535
config["sram_write_sched_gen_sched_addr_gen_strides_5"] = 65535
# configuration registers passed through from top level
for key, value in config.items():
setattr(tester.circuit, key, value)
tester.circuit.clk = 0
tester.circuit.rst_n = 1
tester.step(2)
tester.circuit.rst_n = 0
tester.step(2)
tester.circuit.rst_n = 1
rand.seed(0)
im_size = 40
num_iters = im_size * im_size
data_in = 0
for i in range(num_iters):
for i in range(4):
setattr(tester.circuit, f'data_in_{i}', data_in + i)
tester.eval()
data_in = data_in + 4
tester.step(2)
with tempfile.TemporaryDirectory() as tempdir:
tester.compile_and_run(target="verilator",
directory=tempdir,
magma_output="verilog",
flags=["-Wno-fatal"])