def geffe_generator(): LFSR1 = Lfsr(initial_state=10101010, taps=(8,)) LFSR2 = Lfsr(initial_state=11001100, taps=(8,)) LFSR3 = Lfsr(initial_state=11110000, taps=(8,)) my_tuple = LFSR1, LFSR2, LFSR3 parse_tree = "xor", "and", "and", 1, 2, "not", 3, 1 for _ in range(8): fullStreamCipher = FullStreamCipher(my_tuple, parse_tree) print(str(LFSR1.state[-1]) + ", " + str(LFSR2.state[-1]) + ", " + str(LFSR3.state[-1]) + " => " + str(fullStreamCipher.shift()))
def elaborate(self, plat): lfsr1 = Lfsr.num_steps(1200) lfsr2 = Lfsr.num_steps(1000, default_enabled=False) led1 = plat.request('led_r') led2 = plat.request('led_g') m = Module() # Use both LFSRs m.d.sync += [ led1.eq(lfsr1.value[0]), led2.eq(lfsr2.value[0]), ] # step lfsr2 when lfsr 1 is about to restart m.d.sync += [lfsr2.enable.eq(watch_lfsr(m, lfsr1, 1199))] m.submodules += [lfsr1, lfsr2] return m
def elaborate(self, plat): lfsr = Lfsr(LfsrConfig.num_bits(11)) led = plat.request('led_r') m = Module() m.d.sync += led.eq(lfsr.value[0]) m.submodules += [lfsr] return m
def elaborate(self, plat): lfsr = Lfsr.num_steps(1100) led = plat.request('led_r') m = Module() m.d.sync += led.eq(lfsr.value[0]) m.d.comb += lfsr.restart.eq(watch_lfsr(m, lfsr, 999)) m.submodules += [lfsr] return m
def __init__(self, n_bits, *, with_enable=False): self.lfsrs = [ Lfsr.num_steps(501 + 7 * i, restart_value=i) for i in range(n_bits) ] self.restart = Signal() # Input self.with_enable = with_enable if with_enable: self.enable = Signal() # Input self.output = Signal(n_bits) # Output
def elaborate(self, plat): # 89.77 90.62 94.95 95.31 95.31 95.31 95.31 95.31 101.58 107.52 lfsr = Lfsr.num_steps(1100, default_enabled=False) button = plat.request('button') led = plat.request('led_r') m = Module() m.d.sync += led.eq(lfsr.value[0]) m.d.comb += lfsr.restart.eq(watch_lfsr(m, lfsr, 999)) m.d.comb += lfsr.enable.eq(button) m.submodules += [lfsr] return m
def __init__(self, params): self.params = params # Internal-ish objects self.x = Lfsr(params.horizontal.lfsr_config) self.y = Lfsr(params.vertical.lfsr_config, False) # Output signals self.at_frame_m1 = Signal(1) # high for 1 cycle just before x=0, y=0 self.at_frame_m2 = Signal( 1) # high for 1 cycle 2 cycles before x=0, y=0 self.at_line_m1 = Signal(1) # high for 1 cycle just before x=0 self.horizontal_sync = Signal(1, reset=not params.sync_positive) self.vertical_sync = Signal(1, reset=not params.sync_positive) self.active = Signal(1, reset=True) # High while in display area self.vertical_blanking = Signal( 1) # From last pixel in display line to first pixels of display self.at_active_line_m1 = Signal( 1) # high for 1 cycle, one cycles before start of an active line self.at_active_line_m2 = Signal( 1) # high for 1 cycle, two cycles before start of an active line # Internal signal self.last_frame_line = Signal(1) # high for entire last line
def make_lfsr(self): return Lfsr.num_steps(self.num_words, default_enabled=False)
def __init__(self): self.m_axis = AxiStream(prefix="m") self.counter = Signal(8) self.lfsr = Lfsr(tap_mask=0x002C)
from nmigen.back import verilog from nmigen.sim import Simulator from lfsr import Lfsr dut = Lfsr() def bench(): yield dut.en.eq(1) for _ in range(100): yield sim = Simulator(dut) sim.add_clock(1e-6) sim.add_sync_process(bench) with sim.write_vcd("lfsr.vcd"): sim.run() with open("lfsr.v", "w") as f: f.write(verilog.convert(dut, ports=[dut.out]))
def prepare_table(): LFSR1 = Lfsr(initial_state=1010, taps=(4,)) LFSR2 = Lfsr(initial_state=1100, taps=(4,)) return LFSR1, LFSR2
def __init__(self): self.s_axis = AxiStream(prefix="s", tuser_bits=100) self.lfsr = Lfsr() self.rx_byte_count = Signal(32)