def process_output(line):
'''
line = 'T0_out_s0t0 -> self.out'
rval = 'OUTPUT tile 0 (0,0) / out_BUS16_S0_T0 / wire_0_0_BUS16_S0_T0'
'''
wire = re.search('(\S+)\s*->\s*self.out', line).group(1)
(tileno, dir, side, track) = cgra_info.parse_canon(wire)
(r, c) = cgra_info.tileno2rc(tileno)
g = cgra_info.canon2global(wire)
return '# OUTPUT tile %d (%d,%d) / %s_BUS16_S%d_T%d / %s' %\
(tileno, r, c, dir, side, track, g)
def process_input(line):
'''
line = 'self.in -> T0_in_s2t0'
rval = 'INPUT tile 0 (0,0) / in_BUS16_S2_T0 / wire_0_m1_BUS16_S0_T0'
'''
wire = re.search('self.in\s*->\s*(\S+)', line).group(1)
# (tileno,lhs) = striptile(wire)
# (tileno,lhs) = cgra_info.parse_resource(wire)
(tileno, dir, side, track) = cgra_info.parse_canon(wire)
(r, c) = cgra_info.tileno2rc(tileno)
g = cgra_info.canon2global(wire)
return '# INPUT tile %d (%d,%d) / %s_BUS16_S%d_T%d / %s' %\
(tileno, r, c, dir, side, track, g)
def process_input(line):
'''
# NOTE in 16x16 grid w/io pads, input can *only* go to tile 0x15 (T21) in_s2t0
line = 'self.in -> T0_in_s2t0'
rval = 'INPUT tile 0 (0,0) / in_BUS16_S2_T0 / wire_0_m1_BUS16_S0_T0'
'''
wire = re.search('self.in\s*->\s*(\S+)', line).group(1)
# (tileno,lhs) = striptile(wire)
# (tileno,lhs) = cgra_info.parse_resource(wire)
assert wire == 'T21_in_s2t0', "\nERROR %s;\n'self.in' can only connect to T21_in_s2t0\n\n" % line
(tileno, dir, side, track) = cgra_info.parse_canon(wire)
(r, c) = cgra_info.tileno2rc(tileno)
g = cgra_info.canon2global(wire)
return '# INPUT tile %d (%d,%d) / %s_BUS16_S%d_T%d / %s' %\
(tileno, r, c, dir, side, track, g)
def found_new_tile(prevtile, thistile):
# Sources for PE inputs (defaults from verilog test_pe.v and test_opt_reg.v)
# print "# TILE %d %s" % (thistile, rc)
# print "####################### TILE %d %s" % (thistile, rc)
if (verbose):
[r,c] = cgra_info.tileno2rc(thistile); rc = "(%d,%d)" % (r,c)
print ""
print " TILE %d %s" % (thistile, rc)
# valid values for e.g. asrc: "wire `op_a_in`" or "reg `op_a_in`" or (deprecated) "0x[0-9]+"
global asrc, bsrc, csrc, dsrc
(asrc, bsrc, csrc, dsrc) = ("reg `op_a_in`", "reg `op_b_in`", "reg `op_c_in`", "reg `op_d_in`")
# Contents of PE input regs
# valid values for e.g. areg: "0x[0-9]+" or 'wireA' or 'unset'
global areg, breg, creg, dreg
(areg, breg, creg, dreg) = ("unset", "unset", "unset", "unset")
def tileno2rc(tileno):
if USE_CGRA_INFO: return cgra_info.tileno2rc(tileno)
else:
return (int(tileno) / 8, int(tileno) % 8)
# if (tmpaddr == "00050009"): DBG = 1
(regs,connections) = cgra_info.sb_decode(e,RR,DDDDDDDD)
if DBG:
print "----------------------------------------"
print connections
print regs
print "----------------------------------------"
# Hm. They have to be printed in a certain order according to bit number
comments = [None]*32
# Want:
# "data[(1, 0)] : @ tile (0, 1) connect wire 3 (pe_out_res) to out_BUS16_S0_T0"
t = thistile
[r,c] = cgra_info.tileno2rc(t); rc = "(%d, %d)" % (r,c);
for outwire in sorted(connections.iterkeys()):
# print outwire + " " + str(connections[outwire])
(inwire,configh,configl,wireno) = connections[outwire]
# HACK HACK FIXME
# if HACK1 => only list connections where wireno != 0
printwire = True
if HACK1:
# FIXME print "HACK1 only printing connections with wireno != 0"
printwire = (wireno != 0)
if (printwire):
# Adjust bits so they fit in their 32-bit register!
(configh,configl) = (configh%32,configl%32)
# if (tmpaddr == "00050009"): DBG = 1
(regs, connections) = cgra_info.sb_decode(e, RR, DDDDDDDD)
if DBG:
print "----------------------------------------"
print connections
print regs
print "----------------------------------------"
# Hm. They have to be printed in a certain order according to bit number
comments = [None] * 32
# Want:
# "data[(1, 0)] : @ tile (0, 1) connect wire 3 (pe_out_res) to out_BUS16_S0_T0"
t = thistile
[r, c] = cgra_info.tileno2rc(t)
rc = "(%d, %d)" % (r, c)
for outwire in sorted(connections.iterkeys()):
# print outwire + " " + str(connections[outwire])
(inwire, configh, configl, wireno) = connections[outwire]
# HACK HACK FIXME
# if HACK1 => only list connections where wireno != 0
printwire = True
if HACK1:
# FIXME print "HACK1 only printing connections with wireno != 0"
printwire = (wireno != 0)
if (printwire):
# Adjust bits so they fit in their 32-bit register!