def test_fifo_ctrl_level_changes(self):
# Verify FIFOCtrl level changes.
dut = _LiteDRAMFIFOCtrl(base=0,
depth=16,
read_threshold=0,
write_threshold=16)
def main_generator():
self.assertEqual((yield dut.level), 0)
# Level
def check_level_diff(write, read, diff):
level = (yield dut.level)
yield dut.write.eq(write)
yield dut.read.eq(read)
yield
yield dut.write.eq(0)
yield dut.read.eq(0)
yield
self.assertEqual((yield dut.level), level + diff)
check_level_diff(write=1, read=0, diff=+1)
check_level_diff(write=1, read=0, diff=+1)
check_level_diff(write=1, read=1, diff=+0)
check_level_diff(write=1, read=1, diff=+0)
check_level_diff(write=0, read=1, diff=-1)
check_level_diff(write=0, read=1, diff=-1)
generators = [
main_generator(),
self.fifo_ctrl_flag_checker(dut,
write_threshold=16,
read_threshold=0),
]
run_simulation(dut, generators)
def test_fifo_ctrl_level_changes(self):
# Verify FIFOCtrl level changes.
dut = _LiteDRAMFIFOCtrl(base=0, depth=16)
def main_generator():
self.assertEqual((yield dut.level), 0)
def check_level_diff(write, read, diff):
level = (yield dut.level)
yield dut.write.eq(write)
yield dut.read.eq(read)
yield
yield dut.write.eq(0)
yield dut.read.eq(0)
yield
self.assertEqual((yield dut.level), level + diff)
check_level_diff(write=1, read=0, diff=+1)
check_level_diff(write=1, read=0, diff=+1)
check_level_diff(write=1, read=1, diff=+0)
check_level_diff(write=1, read=1, diff=+0)
check_level_diff(write=0, read=1, diff=-1)
check_level_diff(write=0, read=1, diff=-1)
run_simulation(dut, main_generator())
def test_fifo_ctrl_address_changes(self):
# Verify FIFOCtrl address changes.
dut = _LiteDRAMFIFOCtrl(base=0, depth=16)
def main_generator():
self.assertEqual((yield dut.write_address), 0)
self.assertEqual((yield dut.read_address), 0)
# Write address
yield dut.write.eq(1)
yield
# Write_address gets updated 1 cycle later
for i in range(24 - 1):
self.assertEqual((yield dut.write_address), i % 16)
yield
yield dut.write.eq(0)
yield
self.assertEqual((yield dut.write_address), 24 % 16)
# Read address
yield dut.read.eq(1)
yield
for i in range(24 - 1):
self.assertEqual((yield dut.read_address), i % 16)
yield
yield dut.read.eq(0)
yield
self.assertEqual((yield dut.read_address), 24 % 16)
run_simulation(dut, main_generator())
def __init__(self):
self.port = LiteDRAMNativeWritePort(address_width=32,
data_width=32)
ctrl = _LiteDRAMFIFOCtrl(base=8, depth=depth)
self.submodules.ctrl = ctrl
writer = _LiteDRAMFIFOWriter(data_width=32,
port=self.port,
ctrl=ctrl)
self.submodules.writer = writer
self.memory = DRAMMemory(32, 128)
assert 8 + sequence_len <= len(self.memory.mem)
def __init__(self):
self.port = LiteDRAMNativeReadPort(address_width=32,
data_width=32)
ctrl = _LiteDRAMFIFOCtrl(base=8, depth=depth)
reader = _LiteDRAMFIFOReader(data_width=32,
port=self.port,
ctrl=ctrl)
self.submodules.ctrl = ctrl
self.submodules.reader = reader
self.memory = DRAMMemory(32,
len(memory_data),
init=memory_data)
assert 8 + sequence_len <= len(self.memory.mem)
def test_fifo_ctrl_address_changes(self):
# Verify FIFOCtrl address changes.
# We are ignoring thresholds (so readable/writable signals)
dut = _LiteDRAMFIFOCtrl(base=0,
depth=16,
read_threshold=0,
write_threshold=16)
def main_generator():
self.assertEqual((yield dut.write_address), 0)
self.assertEqual((yield dut.read_address), 0)
# Write address
yield dut.write.eq(1)
yield
# Write_address gets updated 1 cycle later
for i in range(24 - 1):
self.assertEqual((yield dut.write_address), i % 16)
yield
yield dut.write.eq(0)
yield
self.assertEqual((yield dut.write_address), 24 % 16)
# Read address
yield dut.read.eq(1)
yield
for i in range(24 - 1):
self.assertEqual((yield dut.read_address), i % 16)
yield
yield dut.read.eq(0)
yield
self.assertEqual((yield dut.read_address), 24 % 16)
generators = [
main_generator(),
self.fifo_ctrl_flag_checker(dut,
write_threshold=16,
read_threshold=0),
]
run_simulation(dut, generators)