class MT8KTF51264(SDRAMModule):
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6 / 8192,
tWTR=(4, 7.5),
tCCD=(4, None),
tRRD=(4, 10))
speedgrade_timings = {
"800":
_SpeedgradeTimings(tRP=13.91,
tRCD=13.91,
tWR=13.91,
tRFC=260,
tFAW=(None, 50),
tRAS=None),
"1066":
_SpeedgradeTimings(tRP=15,
tRCD=15,
tWR=15,
tRFC=86,
tFAW=(None, 50),
tRAS=None),
"1333":
_SpeedgradeTimings(tRP=15,
tRCD=15,
tWR=15,
tRFC=107,
tFAW=(None, 45),
tRAS=None),
}
speedgrade_timings["default"] = speedgrade_timings["1333"]
class MTA4ATF1G64HZ(DDR4Module):
# geometry
ngroupbanks = 4
ngroups = 2
nbanks = ngroups * ngroupbanks
nrows = 128 * 1024
ncols = 1024
# timings
trefi = {
"1x": 64e6 / 8192,
"2x": (64e6 / 8192) / 2,
"4x": (64e6 / 8192) / 4
}
trfc = {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
technology_timings = _TechnologyTimings(tREFI=trefi,
tWTR=(4, 7.5),
tCCD=(4, 6.25),
tRRD=(4, 7.5),
tZQCS=(128, None))
speedgrade_timings = {
"2666":
_SpeedgradeTimings(tRP=13.75,
tRCD=13.75,
tWR=15,
tRFC=trfc,
tFAW=(28, 30),
tRAS=32),
}
speedgrade_timings["default"] = speedgrade_timings["2666"]
class M12L64322A(SDRAMModule):
memtype = "SDR"
# geometry
nbanks = 4
nrows = 2048
ncols = 256
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
def __init__(self, clk_freq, sdram_rate):
# The datasheet specifies tWr in clock cycles, not in
# ns but to me it looks like litedram expects
# ns for these two parameters, so I have to convert them
# to ns first.
tWr = self.clock_cycles_to_ns(2, clk_freq, sdram_rate)
tRRD = self.clock_cycles_to_ns(2, clk_freq, sdram_rate)
self.technology_timings = _TechnologyTimings(tREFI=64e6/8000, tWTR=(2, None), tCCD=(1, None), tRRD=(None, tRRD))
self.speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=tWr, tRFC=(None, 60), tFAW=None, tRAS=42)}
super().__init__(clk_freq, sdram_rate)
class MT41K64M16(SDRAMModule):
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 8192
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6 / 8192,
tWTR=(4, 7.5),
tCCD=(4, None),
tRRD=(4, 10))
speedgrade_timings = {
"800":
_SpeedgradeTimings(tRP=13.1,
tRCD=13.1,
tWR=13.1,
tRFC=64,
tFAW=(None, 50),
tRAS=37.5),
"1066":
_SpeedgradeTimings(tRP=13.1,
tRCD=13.1,
tWR=13.1,
tRFC=86,
tFAW=(None, 50),
tRAS=37.5),
"1333":
_SpeedgradeTimings(tRP=13.5,
tRCD=13.5,
tWR=13.5,
tRFC=107,
tFAW=(None, 45),
tRAS=36),
"1600":
_SpeedgradeTimings(tRP=13.75,
tRCD=13.75,
tWR=13.75,
tRFC=128,
tFAW=(None, 40),
tRAS=35),
}
speedgrade_timings["default"] = speedgrade_timings["1600"]