def __init__(self, sys_clk_freq=int(100e6), with_vga=False, **kwargs):
platform = ego1.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on EGO1 Board",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# VGA terminal -----------------------------------------------------------------------------
if with_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[4:8]),
vga_pads.green.eq(terminal.green[4:8]),
vga_pads.blue.eq(terminal.blue[4:8])
]
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(50e6),
with_mister_sdram=True,
with_mister_vga=False,
sdram_rate="1:1",
**kwargs):
platform = de10nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE10-Nano",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_sdram=with_mister_sdram,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if with_mister_sdram and not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M16(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# VGA terminal -----------------------------------------------------------------------------
if with_mister_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal",
self.terminal.bus,
region=SoCRegion(origin=0x30000000,
size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[2:8]),
vga_pads.green.eq(terminal.green[2:8]),
vga_pads.blue.eq(terminal.blue[2:8])
]
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
platform = de10lite.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE10-Lite",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16320(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# VGA Terminal -----------------------------------------------------------------------------
if with_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal",
self.terminal.bus,
region=SoCRegion(origin=0x30000000,
size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync_n.eq(terminal.vsync),
vga_pads.hsync_n.eq(terminal.hsync),
vga_pads.r.eq(terminal.red[4:8]),
vga_pads.g.eq(terminal.green[4:8]),
vga_pads.b.eq(terminal.blue[4:8])
]
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# create VGA terminal
self.submodules.terminal = terminal = Terminal()
self.add_wb_slave(self.mem_map["terminal"], self.terminal.bus)
self.add_memory_region("terminal", self.mem_map["terminal"], 0x10000)
# connect VGA pins
vga = self.platform.request('vga_out', 0)
self.comb += [
vga.vsync_n.eq(terminal.vsync),
vga.hsync_n.eq(terminal.hsync),
vga.r.eq(terminal.red[4:8]),
vga.g.eq(terminal.green[4:8]),
vga.b.eq(terminal.blue[4:8])
]
def __init__(self,
sys_clk_freq=int(75e6),
with_ethernet=False,
with_vga=False,
**kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys4DDR",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR2",
nphases=2,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT47H64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# VGA terminal -----------------------------------------------------------------------------
if with_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal",
self.terminal.bus,
region=SoCRegion(origin=0x30000000,
size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[4:8]),
vga_pads.green.eq(terminal.green[4:8]),
vga_pads.blue.eq(terminal.blue[4:8])
]
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")