Subsignal("clk_n", Pins("AW38"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("AV38"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("AR33"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("BC31 AY27 BB26 BD26 AP30 BF39 AR30 BA32"),
IOStandard("POD12_DCI")),
Subsignal(
"dq",
Pins("BB31 BB32 AY33 AY32 BC33 BC32 BB34 BC34",
"AT28 AT27 AU27 AV27 AV28 AV29 AW30 AY30",
"BA28 BA27 AW28 AW29 BC27 BB27 BA29 BB29",
"BE28 BF28 BE30 BD30 BF27 BE27 BF29 BF30",
"AT32 AU32 AM30 AL30 AR31 AN31 AR32 AN32",
"BD40 BD39 BF42 BF43 BF41 BE40 BE37 BF37",
"AM27 AN27 AP28 AP29 AM29 AN29 AR28 AR27",
"AW34 AV32 AV31 AV34 BA35 BA34 AW31 AY31"),
IOStandard("POD12_DCI"), Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("BB36 AU30 BB30 BD29 AM32 BF38 AL29 AW33"),
IOStandard("DIFF_POD12"),
Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("BB35 AU29 BA30 BD28 AM31 BE38 AL28 AV33"),
IOStandard("DIFF_POD12"),
Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AU31"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST")),
(
Subsignal("clk_n", Pins("AW38"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("AV38"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("AR33"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("BC31 AY27 BB26 BD26 AP30 BF39 AR30 BA32"),
IOStandard("POD12_DCI")),
Subsignal(
"dq",
Pins("BB31 BB32 AY33 AY32 BC33 BC32 BB34 BC34",
"AT28 AT27 AU27 AV27 AV28 AV29 AW30 AY30",
"BA28 BA27 AW28 AW29 BC27 BB27 BA29 BB29",
"BE28 BF28 BE30 BD30 BF27 BE27 BF29 BF30",
"AT32 AU32 AM30 AL30 AR31 AN31 AR32 AN32",
"BD40 BD39 BF42 BF43 BF41 BE40 BE37 BF37",
"AM27 AN27 AP28 AP29 AM29 AN29 AR28 AR27",
"AW34 AV32 AV31 AV34 BA35 BA34 AW31 AY31"),
IOStandard("POD12_DCI"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("BB36 AU30 BB30 BD29 AM32 BF38 AL29 AW33"),
IOStandard("DIFF_POD12"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("BB35 AU2 BA30 BD28 AM31 BE38 AL28 AV33"),
IOStandard("DIFF_POD12"), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AU31"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST")),
(
"ddram",
1,
Subsignal(
"a",
Pins("AN24 AT24 AW24 AN26 AY22 AY23 AV24 BA22",
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
analyzer_csv="analyzer.csv",
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
kwargs["integrated_rom_size"] = 0x10000 if with_etherbone else 0x8000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
_dws1000_ardu_io = [
("dw1000_spi", 0,
Subsignal("clk", Pins("ck_io:ck_io13")),
Subsignal("mosi", Pins("ck_io:ck_io11")),
Subsignal("cs_n", Pins("ck_io:ck_io10")),
Subsignal("miso", Pins("ck_io:ck_io12")),
Subsignal("pha", Pins("ck_io:ck_io0"), Misc("PULLDOWN True")),
Subsignal("pol", Pins("ck_io:ck_io1"), Misc("PULLDOWN True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("dw1000_led", 0, Pins("ck_io:ck_io3"), IOStandard("LVCMOS33")), # TX LED on the DWS1000 module
("dw1000_led", 1, Pins("ck_io:ck_io4"), IOStandard("LVCMOS33")), # RX LED on the DWS1000 module
("dw1000_info", 0,
Subsignal("exton", Pins("ck_io:ck_a0")),
Subsignal("wakeup", Pins("ck_io:ck_io9")),
Subsignal("irq", Pins("ck_io:ck_io8")),
IOStandard("LVCMOS33"),
),
("dw1000_rstn", 0,
Pins("ck_io:ck_io7"),
IOStandard("LVCMOS33"),
),
]
platform.add_extension(_dws1000_ardu_io)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("dw1000_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
self.submodules.dw1000_rstn = GPIOTristate(platform.request("dw1000_rstn", 0))
self.add_csr("dw1000_rstn")
self.submodules.dw1000_info = GPIOIn(platform.request("dw1000_info"))
self.add_csr("dw1000_info")
# SPI with LiteScope
self.add_spi_master()
print(dir(self.cpu.ibus))
analyzer_signals = [
self.spi_master._control.storage,
self.spi_master._status.status,
self.spi_master._cs.storage,
self.spi_master.mosi,
self.spi_master.miso,
self.spi_master.pads.clk,
self.spi_master.pads.cs_n,
self.spi_master.pads.mosi,
self.spi_master.pads.miso,
self.dw1000_rstn._oe.storage,
self.dw1000_rstn._in.status,
self.dw1000_rstn._out.storage,
self.dw1000_info._in.status,
self.cpu.ibus.adr,
self.cpu.ibus.stb,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=1024,
clock_domain="sys",
csr_csv=analyzer_csv
)
self.add_csr("analyzer")
Subsignal("ba", Pins("B5 A4")),
Subsignal("cs_n", Pins("A3")),
# CKE not connected on XS 2.2/2.4
Subsignal("cke", Pins("B3")),
Subsignal("ras_n", Pins("E9")),
Subsignal("cas_n", Pins("A6")),
Subsignal("we_n", Pins("A5")),
Subsignal(
"dq",
Pins("F14 G15 F15 H15 G13 A13 H14 B13",
"C13 C8 B12 B8 F13 C12 B11 E13"),
),
# DQML/DQMH not connected on XS 2.2/2.4
Subsignal("dm", Pins("AB27 AA26")),
IOStandard("3.3-V LVTTL"),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
),
# DDR3 SDRAM
("ddram", 0,
Subsignal(
"a",
Pins("AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13",
"AH13 AH14 AJ9 AK9 AK7 AK8 AG12"),
IOStandard("SSTL15"),
), Subsignal(
"ba",
Pins("AH10 AJ11 AK11"),
IOStandard("SSTL-15 CLASS I"),
), Subsignal("ras_n", Pins("AH8"), IOStandard("SSTL-15 CLASS I")),
Subsignal("cas_n", Pins("AH7"), IOStandard("SSTL-15 CLASS I")),
# Support for the Fomu
# More information can be found here https://github.com/im-tomu/foboot.git
from litex.build.lattice.platform import LatticePlatform
from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal
_io_evt = [("serial", 0, Subsignal("rx", Pins("21")),
Subsignal("tx", Pins("13"),
Misc("PULLUP")), IOStandard("LVCMOS33")),
("usb", 0, Subsignal("d_p",
Pins("34")), Subsignal("d_n", Pins("37")),
Subsignal("pullup", Pins("35")), Subsignal("pulldown", Pins("36")),
IOStandard("LVCMOS33")),
(
"touch",
0,
Subsignal("t1", Pins("48"), IOStandard("LVCMOS33")),
Subsignal("t2", Pins("47"), IOStandard("LVCMOS33")),
Subsignal("t3", Pins("46"), IOStandard("LVCMOS33")),
Subsignal("t4", Pins("45"), IOStandard("LVCMOS33")),
),
(
"pmoda",
0,
Subsignal("p1", Pins("28"), IOStandard("LVCMOS33")),
Subsignal("p2", Pins("27"), IOStandard("LVCMOS33")),
Subsignal("p3", Pins("26"), IOStandard("LVCMOS33")),
Subsignal("p4", Pins("23"), IOStandard("LVCMOS33")),
),
(
"pmodb",
from sys import path
from migen import *
from migen.build.xilinx.common import *
from litex.soc.interconnect.csr import *
from litex.soc.cores.freqmeter import FreqMeter
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from litex.build.generic_platform import Subsignal, Pins, IOStandard, Misc
from .s7_iserdes import S7_iserdes
from common import LedBlinker, myzip
ltc_pads = [
("LTC_SPI", 0,
Subsignal("cs_n", Pins("LPC:LA14_P")),
Subsignal("miso", Pins("LPC:LA14_N"), Misc("PULLUP TRUE")),
Subsignal("mosi", Pins("LPC:LA27_P")),
Subsignal("clk", Pins("LPC:LA27_N")),
IOStandard("LVCMOS25")
),
("LTC_OUT", 0, # Bank 0
Subsignal("a_p", Pins("LPC:LA03_P")),
Subsignal("a_n", Pins("LPC:LA03_N")),
Subsignal("b_p", Pins("LPC:LA08_P")),
Subsignal("b_n", Pins("LPC:LA08_N")),
IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE")
),
("LTC_OUT", 1, # Bank 0
Subsignal("a_p", Pins("LPC:LA12_P")),
Subsignal("a_n", Pins("LPC:LA12_N")),
from rtl.reboot import Reboot
from rtl.spi_ram import SpiRamQuad
from rtl.spi_ram_dual import SpiRamDualQuad
from rtl.version import Version
from rtl.picorvspi import PicoRVSpi
import lxsocdoc
_io = [
("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")),
("programn", 0, Pins("R1"), IOStandard("LVCMOS33")),
(
"serial",
0,
Subsignal("rx", Pins("U2"), IOStandard("LVCMOS33"),
Misc("PULLMODE=UP")),
Subsignal("tx", Pins("U1"), IOStandard("LVCMOS33")),
),
("led", 0, Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"),
IOStandard("LVCMOS33")), # Anodes
("led", 1, Pins("P19 L18 K18"),
IOStandard("LVCMOS33")), # Cathodes via FET
("usb", 0, Subsignal("d_p", Pins("F3")), Subsignal("d_n", Pins("G3")),
Subsignal("pullup",
Pins("E4")), Subsignal("vbusdet",
Pins("F4")), IOStandard("LVCMOS33")),
(
"keypad",
0,
Subsignal("left", Pins("G2"), Misc("PULLMODE=UP")),
Subsignal("right", Pins("F2"), Misc("PULLMODE=UP")),
0,
Subsignal("a",
Pins("B14 C8 A14 C14 C9 B10 D9 A12 D8 A13 B12 A9 A8 B11"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("C16 A15 B15"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("B16"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("C11"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("C12"), IOStandard("SSTL135")),
# cs_n is hardwired on the board
#Subsignal("cs_n", Pins("-"), IOStandard("SSTL135")),
Subsignal("dm", Pins("F12 H11"), IOStandard("SSTL135")),
Subsignal(
"dq",
Pins("F15 F13 E16 D11 E12 E13 D16 E11",
"G12 J16 G16 J15 H14 H12 H16 H13"), IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("D14 G14"), IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("D15 F14"), IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("B9"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("A10"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("D13"), IOStandard("SSTL135")),
Subsignal("odt", Pins("C13"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("E15"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
]
# The connectors are named after the daughterboard, not the core board
# because on the different core boards the names vary, but on the
# DDR3 SDRAM
(
"ddram",
0,
Subsignal("a", Pins("U2 R4 V2 V4 T3 R7 V6 T6", "U7 V7 P6 T5 R6 U6"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("V5 T1 U3"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("U1"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("V3"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("P7"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("R3"), IOStandard("SSTL135")),
Subsignal("dm", Pins("K4 M3"), IOStandard("SSTL135")),
Subsignal("dq",
Pins("K2 K3 L4 M6 K6 M4 L5 L6", "N4 R1 N1 N5 M2 P1 M1 P2"),
IOStandard("SSTL135"), Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("K1 N3"), IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("L1 N2"), IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("R5"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("T4"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("T2"), IOStandard("SSTL135")),
Subsignal("odt", Pins("P5"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("J6"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
]
# Connectors ---------------------------------------------------------------------------------------
#from gateware import cas
from gateware import spi_flash
serial = [
("serial", 0,
Subsignal("rx", Pins("GPIO:0")), # Pin 1 - A2 - Silkscreen 1
Subsignal("tx", Pins("GPIO:1")), # Pin 2 - A1 - Silkscreen 2
IOStandard("LVCMOS33")
)
]
reset_button = [
# Reset shorts these two pins together
# Pin 12 - Silkscreen 12
("reset", 0, Pins("GPIO:11"), IOStandard("LVCMOS33"), Misc("PullUp")),
# Pin 13 - Silkscreen 13
("reset_out", 0, Pins("GPIO:12"), IOStandard("LVCMOS33")),
]
class _CRG(Module):
def __init__(self, platform):
clk16 = platform.request("clk16")
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain() #reset_less=True)
self.reset = Signal()
# Reset signal goes high to reset.
Subsignal("clk_p", Pins("BH46"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
Subsignal(
"dq",
Pins("BN32 BP32 BL30 BM30 BP29 BP28 BP31 BN31",
"BJ31 BH31 BF32 BF33 BH29 BH30 BF31 BG32",
"BK31 BL31 BK33 BL33 BL32 BM33 BN34 BP34",
"BH34 BH35 BF35 BF36 BJ33 BJ34 BG34 BG35",
"BM52 BL53 BL52 BL51 BN50 BN51 BN49 BM48",
"BE50 BE49 BE51 BD51 BF52 BF51 BG50 BF50",
"BH50 BJ51 BH51 BH49 BK50 BK51 BJ49 BJ48",
"BN44 BN45 BM44 BM45 BP43 BP44 BN47 BP47"),
# ECC excluded 8 pins
# "BG54 BG53 BE53 BE54 BH52 BG52 BK54 BK53"
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal(
"dqs_n",
Pins("BN30 BM29 BK30 BG30 BM35 BN35 BK35 BJ32",
"BM50 BP49 BF48 BG49 BJ47 BK49 BP46 BP42"), #"BJ54 BJ53"
IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal(
"dqs_p",
Pins("BN29 BM28 BJ29 BG29 BL35 BM34 BK34 BH32",
"BM49 BP48 BF47 BG48 BH47 BK48 BN46 BN42"), #"BH54 BJ52"
IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
from valentyusb.usbcore import io as usbio
from rtl.crg import _CRG
from rtl.messible import Messible
from rtl.reboot import Reboot
from rtl.spi_ram import SpiRamQuad
from rtl.version import Version
import lxsocdoc
_io = [
("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")),
("programn", 0, Pins("R1"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("rx", Pins("U2"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("U1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
),
("led", 1, Pins("E3"), IOStandard("LVCMOS33")),
("led", 2, Pins("D3"), IOStandard("LVCMOS33")),
("led", 3, Pins("C3"), IOStandard("LVCMOS33")),
("led", 4, Pins("C4"), IOStandard("LVCMOS33")),
("led", 5, Pins("C2"), IOStandard("LVCMOS33")),
("led", 6, Pins("B1"), IOStandard("LVCMOS33")),
("led", 7, Pins("B20"), IOStandard("LVCMOS33")),
("led", 8, Pins("B19"), IOStandard("LVCMOS33")),
("led", 9, Pins("A18"), IOStandard("LVCMOS33")),
("led", 10, Pins("K20"), IOStandard("LVCMOS33")),
("led", 11, Pins("K19"), IOStandard("LVCMOS33")),
("usb", 0,
Subsignal("d_p", Pins("F3")),
Subsignal("d_n", Pins("G3")),
from modules.rgb import RGB
from modules.analog import AnalogSense
from modules.csr_cdc import CSRClockDomainWrapper
from modules.io_block import IOPort
from litex.soc.cores import spi_flash
from litex.soc.cores.gpio import GPIOTristate, GPIOOut, GPIOIn
from valentyusb.usbcore import io as usbio
# connect all remaninig GPIO pins out
extras = [(
"gpio", 0,
Pins(
"GPIO:0 GPIO:1 GPIO:5 GPIO:6 GPIO:9 GPIO:10 GPIO:11 GPIO:12 GPIO:13 GPIO:18 GPIO:19 GPIO:20 GPIO:21"
), IOStandard("LVCMOS33"), Misc("PULLMODE=DOWN")),
("analog", 0, Subsignal("mux", Pins("F4 F3 F2 H1")),
Subsignal("enable", Pins("F1")), Subsignal("ctrl", Pins("G1")),
Subsignal("sense_p", Pins("H3"), IOStandard("LVCMOS33D")),
Subsignal("sense_n", Pins("G3")), IOStandard("LVCMOS33"))]
# CRG ---------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain()
from litedram.phy import a7ddrphy
from litedram.core import ControllerSettings
from gateware import cas
from gateware import info
from gateware import led
from gateware import spi_flash
from targets.utils import csr_map_update, period_ns
from targets.arty.base import BaseSoC
i2c_pmod_d = [
(
"i2c_pmodd",
0,
Subsignal("scl", Pins("F3"), Misc("PULLUP")),
Subsignal("sda", Pins("D3"), Misc("PULLUP")),
Subsignal("scl_pup", Pins("A14")),
Subsignal("sda_pup", Pins("A13")),
IOStandard("LVCMOS33"),
),
]
class TFSoC(BaseSoC):
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
BaseSoC.__init__(self, platform, spiflash, **kwargs)
platform.add_extension(i2c_pmod_d)
# i2c master
i2c_pads = platform.request("i2c_pmodd", 0)
self.submodules.i2c0 = I2CMaster(i2c_pads)
IOStandard("LVCMOS33")),
# SRAM
(
"issiram",
0,
Subsignal(
"addr",
Pins("M18 M19 K17 N17 P17 P18 R18 W19",
"U19 V19 W18 T17 T18 U17 U18 V16", "W16 W17 V15"),
IOStandard("LVCMOS33")),
Subsignal("data", Pins("W15 W13 W14 U15 U16 V13 V14 U14"),
IOStandard("LVCMOS33")),
Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")),
Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")),
Misc("SLEW=FAST"),
),
# SPIFlash
(
"spiflash",
0,
Subsignal("cs_n", Pins("K19")),
Subsignal("clk", Pins("E19")),
Subsignal("mosi", Pins("D18")),
Subsignal("miso", Pins("D19")),
Subsignal("wp", Pins("G18")),
Subsignal("hold", Pins("F18")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, Subsignal("cs_n",
from sys import argv, exit
from litex.soc.integration.builder import Builder
from litex import RemoteClient
from os import system
from struct import pack, unpack
# from numpy import *
# from matplotlib.pyplot import *
# from scipy.signal import *
from migen import *
from litex.build.generic_platform import Subsignal, Pins, IOStandard, Misc
ltc_pads = [
("LTC_SPI", 0, Subsignal("cs_n", Pins("LPC:LA14_P")),
Subsignal("miso", Pins("LPC:LA14_N"),
Misc("PULLUP TRUE")), Subsignal("mosi", Pins("LPC:LA27_P")),
Subsignal("clk", Pins("LPC:LA27_N")), IOStandard("LVCMOS25")),
(
"LTC_OUT",
0, # Bank 0
Subsignal("a_p", Pins("LPC:LA03_P")),
Subsignal("a_n", Pins("LPC:LA03_N")),
Subsignal("b_p", Pins("LPC:LA08_P")),
Subsignal("b_n", Pins("LPC:LA08_N")),
IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE")),
(
"LTC_OUT",
1, # Bank 0
Subsignal("a_p", Pins("LPC:LA12_P")),
Subsignal("a_n", Pins("LPC:LA12_N")),
Subsignal("b_p", Pins("LPC:LA16_P")),
def __init__(self, io_standard) -> None:
"""
because the board can be used with FPGAs core boards from
different vendors, the constructor needs the vendor specific IOStandard
"""
self.io = [
("serial", 0, Subsignal("rx", Pins("J2:15")),
Subsignal("tx", Pins("J2:16")), io_standard),
("user_led", 0, Pins("J2:40"), io_standard),
("user_led", 1, Pins("J2:39"), io_standard),
("user_led", 2, Pins("J2:38"), io_standard),
("user_led", 3, Pins("J2:37"), io_standard),
("user_led", 4, Pins("J2:36"), io_standard),
("user_btn", 0, Pins("J3:7"), io_standard),
("user_btn", 1, Pins("J2:44"), io_standard),
("user_btn", 2, Pins("J2:43"), io_standard),
("user_btn", 3, Pins("J2:42"), io_standard),
("user_btn", 4, Pins("J2:41"), io_standard),
# GMII Ethernet
("eth_clocks", 0, Subsignal("tx", Pins("J3:22")),
Subsignal("gtx",
Pins("J3:29")), Subsignal("rx",
Pins("J3:37")), io_standard),
(
"eth",
0,
# rst is hardwired on the board
#Subsignal("rst_n", Pins("-")),
Subsignal("int_n", Pins("J3:26")),
Subsignal("mdio", Pins("J3:15")),
Subsignal("mdc", Pins("J3:16")),
Subsignal("rx_dv", Pins("J3:42")),
Subsignal("rx_er", Pins("J3:32")),
Subsignal(
"rx_data",
Pins("J3:41 J3:40 J3:39 J3:38 J3:36 J3:35 J3:34 J3:33")),
Subsignal("tx_en", Pins("J3:28")),
Subsignal("tx_er", Pins("J3:17")),
Subsignal(
"tx_data",
Pins("J3:27 J3:25 J3:24 J3:23 J3:21 J3:20 J3:19 J3:18")),
Subsignal("col", Pins("J3:31")),
Subsignal("crs", Pins("J3:30")),
io_standard),
# Seven Segment
("seven_seg_ctl", 0, Pins("J2:33"), io_standard),
("seven_seg_ctl", 1, Pins("J2:27"), io_standard),
("seven_seg_ctl", 2, Pins("J2:35"), io_standard),
("seven_seg", 0,
Pins("J2:31 J2:26 J2:28 J2:32 J2:34 J2:29 J2:25 J2:30"),
io_standard),
# VGA
("vga", 0, Subsignal("hsync_n", Pins("J3:44")),
Subsignal("vsync_n", Pins("J3:43")),
Subsignal("r", Pins("J3:57 J3:56 J3:59 J3:58 J3:60")),
Subsignal("g", Pins("J3:51 J3:50 J3:53 J3:52 J3:54 J3:55")),
Subsignal("b",
Pins("J3:46 J3:45 J3:48 J3:47 J3:49")), io_standard),
# PullUp resistors are on the board, so we don't need them in the FPGA
(
"sdcard",
0,
Subsignal("data", Pins("J3:10 J3:9 J3:14 J3:13")),
Subsignal("cmd", Pins("J3:12")),
Subsignal("clk", Pins("J3:11")),
Subsignal("cd", Pins("J3:8")),
Misc("SLEW=FAST"),
io_standard,
),
]
def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
platform = de0nano.Platform()
platform.toolchain.additional_qsf_commands = [
'set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"',
]
platform.toolchain.additional_sdc_commands = [
'create_clock -name eth_rx_clk -period 20 [get_ports eth_clocks_ref_clk]',
'create_clock -name eth_rx_clk_virt -period 20',
'derive_clock_uncertainty',
'set CLKAs_max 0.0',
'set CLKAs_min 0.0',
'set CLKAd_max 1.13',
'set CLKAd_min 0.87',
'set tCOa_max 16',
'set tCOa_min 1',
'set BDa_max 1.13',
'set BDa_min 0.87',
'set_input_delay -clock eth_rx_clk_virt -max [expr $CLKAs_max + $tCOa_max + $BDa_max - $CLKAd_min] [get_ports {eth_rx_data[*] eth_crs_dv}]',
'set_input_delay -clock eth_rx_clk_virt -min [expr $CLKAs_min + $tCOa_min + $BDa_min - $CLKAd_max] [get_ports {eth_rx_data[*] eth_crs_dv}]',
]
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE0-Nano",
ident_version=True,
cpu_type="vexriscv_smp",
cpu_variant="linux",
max_sdram_size=0x40000000, # Limit mapped SDRAM to 1GB.
**kwargs)
# Add linker region for OpenSBI
self.add_memory_region("opensbi",
self.mem_map["main_ram"] + 0x00f00000,
0x80000,
type="cached+linker")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# UART -------------------------------------------------------------------------------------
_uart_jp_ios = [("uart", 0,
Subsignal("tx", Pins("JP1:34"),
IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("JP1:32"),
IOStandard("3.3-V LVTTL")))]
self.platform.add_extension(_uart_jp_ios)
self.add_uart(name="uart", baudrate=921600, fifo_depth=1024)
# Leds -------------------------------------------------------------------------------------
led_pads = platform.request_all("user_led")
self.submodules.leds = GPIOOut(led_pads)
self.add_constant("LEDS_NGPIO", len(led_pads))
# Keys -------------------------------------------------------------------------------------
switches_pads = self.platform.request_all("key")
self.submodules.switches = GPIOIn(pads=switches_pads, with_irq=True)
self.irq.add("switches", use_loc_if_exists=True)
self.add_constant("SWITCHES_NGPIO", len(switches_pads))
# RMII Ethernet ----------------------------------------------------------------------------
_ethernet_jp_ios = [
(
"eth_clocks",
0,
Subsignal("ref_clk", Pins("JP2:34")),
IOStandard("3.3-V LVTTL"),
),
(
"eth",
0,
#Subsignal("rst_n", Pins("")),
Subsignal("rx_data", Pins("JP2:36 JP2:35")),
Subsignal("crs_dv", Pins("JP2:33")),
Subsignal("tx_en", Pins("JP2:38")),
Subsignal("tx_data", Pins("JP2:37 JP2:40")),
Subsignal("mdc", Pins("JP2:31")),
Subsignal("mdio", Pins("JP2:32")),
#Subsignal("rx_er", Pins("")),
#Subsignal("int_n", Pins("")),
IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_ethernet_jp_ios)
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
refclk_cd=None,
)
self.add_ethernet(phy=self.ethphy, nrxslots=4, ntxslots=2)
# SD Card ----------------------------------------------------------------------------------
_sdcard_jp_ios = [
(
"sdcard",
0,
Subsignal("data", Pins("JP2:14 JP2:24 JP2:22 JP2:20"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("cmd", Pins("JP2:16"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("clk", Pins("JP2:18")),
Subsignal("cd", Pins("JP2:26")),
Misc("FAST_OUTPUT_REGISTER ON"),
IOStandard("3.3-V LVTTL"),
),
]
#_sdcard_jp_ios = [
# ("spisdcard", 0,
# Subsignal("miso", Pins("JP2:14"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("mosi", Pins("JP2:16"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("clk", Pins("JP2:18")),
# Subsignal("cs_n", Pins("JP2:20"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Misc("FAST_OUTPUT_REGISTER ON"),
# IOStandard("3.3-V LVTTL"),
# ),
#]
self.platform.add_extension(_sdcard_jp_ios)
self.add_sdcard()
#self.add_spi_sdcard()
# EPCS ------------------------------------------------------------------------------------
_spi_flash_ios = [
("spiflash", 0, Subsignal("miso", Pins("H2")),
Subsignal("clk", Pins("H1")), Subsignal("cs_n", Pins("D2")),
Subsignal("mosi", Pins("C1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_spi_flash_ios)
self.add_spi_flash(mode="1x", dummy_cycles=8)
# I2C ADXL345 -----------------------------------------------------------------------------
_i2c_ios = [
("i2c_onboard", 0, Subsignal("scl", Pins("F2")),
Subsignal("sda", Pins("F1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_i2c_ios)
self.submodules.i2c0 = I2CMaster(
self.platform.request("i2c_onboard", 0))
adxl_pads = self.platform.request("acc")
self.comb += adxl_pads.cs_n.eq(1)
# ADC -------------------------------------------------------------------------------------
_spi_ios = [("adc128s", 0, Subsignal("cs_n", Pins("A10")),
Subsignal("mosi",
Pins("B10")), Subsignal("clk", Pins("B14")),
Subsignal("miso", Pins("A9")), IOStandard("3.3-V LVTTL"))]
self.platform.add_extension(_spi_ios)
spi_pads = self.platform.request("adc128s")
self.submodules.spi = SPIMaster(spi_pads, 8, self.clk_freq, 1e6)
self.add_csr("spi")
# interrupts ------------------------------------------------------------------------------
#_interrupts_jp_ios = [
# ("interrupt", 0, Pins("JP2:1"), IOStandard("3.3-V LVTTL")),
# ("interrupt", 1, Pins("JP2:26"), IOStandard("3.3-V LVTTL")),
#]
#self.platform.add_extension(_interrupts_jp_ios)
#interrupts_pads = self.platform.request_all("interrupt")
interrupts_pads = adxl_pads.int
self.submodules.interrupts = GPIOIn(interrupts_pads, with_irq=True)
self.irq.add("interrupts", use_loc_if_exists=True)
self.add_constant("INTERRUPTS_NGPIO", len(interrupts_pads))
