def __init__(self, pads): self.sink = sink = stream.Endpoint(eth_phy_description(8)) # # # tx_ctl_oddrx1f = Signal() tx_data_oddrx1f = Signal(4) self.specials += [ DDROutput(clk=ClockSignal("eth_tx"), i1=sink.valid, i2=sink.valid, o=tx_ctl_oddrx1f), Instance("DELAYG", p_DEL_MODE="SCLK_ALIGNED", p_DEL_VALUE=0, i_A=tx_ctl_oddrx1f, o_Z=pads.tx_ctl) ] for i in range(4): self.specials += [ DDROutput(clk=ClockSignal("eth_tx"), i1=sink.data[i], i2=sink.data[4 + i], o=tx_data_oddrx1f[i]), Instance("DELAYG", p_DEL_MODE="SCLK_ALIGNED", p_DEL_VALUE=0, i_A=tx_data_oddrx1f[i], o_Z=pads.tx_data[i]) ] self.comb += sink.ready.eq(1)
def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True): self.sink = sink = stream.Endpoint(video_data_layout) # # # # Always ack Sink, no backpressure. self.comb += sink.ready.eq(1) # Drive Clk. if hasattr(pads, "clk"): if with_clk_ddr_output: self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain)) else: self.comb += pads.clk.eq(ClockSignal(clock_domain)) # Drive Controls. if hasattr(pads, "de"): self.specials += SDROutput(i=sink.de, o=pads.de, clk=ClockSignal(clock_domain)) if hasattr(pads, "hsync_n") and hasattr(pads, "vsync_n"): self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain)) else: self.specials += SDROutput(i=sink.hsync, o=pads.hsync, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.vsync, o=pads.vsync, clk=ClockSignal(clock_domain)) # Drive Datas. cbits = len(pads.r) cshift = (8 - cbits) for i in range(cbits): self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
def __init__(self, clock_pads, pads, with_hw_init_reset): self._reset = CSRStorage() # # # self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() self.comb += [ self.cd_eth_rx.clk.eq(ClockSignal("eth")), self.cd_eth_tx.clk.eq(ClockSignal("eth")) ] self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx")) reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: self.comb += reset.eq(self._reset.storage) self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), AsyncResetSynchronizer(self.cd_eth_rx, reset), ]
def __init__(self, pads, clock_domain="sys"): self.sink = sink = stream.Endpoint(video_data_layout) # # # # Always ack Sink, no backpressure. self.comb += sink.ready.eq(1) # Clocking + Differential Signaling. pads_clk = Signal() self.specials += DDROutput(i1=1, i2=0, o=pads_clk, clk=ClockSignal(clock_domain)) self.specials += Instance("OBUFDS", i_I=pads_clk, o_O=pads.clk_p, o_OB=pads.clk_n) # Encode/Serialize Datas. for color in ["r", "g", "b"]: # TMDS Encoding. encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder()) self.submodules += encoder self.comb += encoder.d.eq(getattr(sink, color)) self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if color == "r" else 0) self.comb += encoder.de.eq(sink.de) # 10:1 Serialization + Differential Signaling. pad_o = Signal() serializer = VideoS7HDMI10to1Serializer( data_i = encoder.out, data_o = pad_o, clock_domain = clock_domain, ) self.submodules += serializer c2d = {"r": 0, "g": 1, "b": 2} pad_p = getattr(pads, f"data{c2d[color]}_p") pad_n = getattr(pads, f"data{c2d[color]}_n") self.specials += Instance("OBUFDS", i_I=pad_o, o_O=pad_p, o_OB=pad_n)
def __init__(self, pads, clock_domain="sys", pn_swap=[]): self.sink = sink = stream.Endpoint(video_data_layout) # # # # Always ack Sink, no backpressure. self.comb += sink.ready.eq(1) # Clocking + Pseudo Differential Signaling. self.specials += DDROutput(i1=1, i2=0, o=pads.clk_p, clk=ClockSignal(clock_domain)) # Encode/Serialize Datas. for color in ["r", "g", "b"]: # TMDS Encoding. encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder()) setattr(self.submodules, f"{color}_encoder", encoder) self.comb += encoder.d.eq(getattr(sink, color)) self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if color == "r" else 0) self.comb += encoder.de.eq(sink.de) # 10:1 Serialization + Pseudo Differential Signaling. c2d = {"r": 0, "g": 1, "b": 2} data = encoder.out if color not in pn_swap else ~encoder.out serializer = VideoHDMI10to1Serializer( data_i = data, data_o = getattr(pads, f"data{c2d[color]}_p"), clock_domain = clock_domain, ) setattr(self.submodules, f"{color}_serializer", serializer)
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # Clk / Rst clk50 = platform.request("clk50") # PLL self.submodules.pll = pll = CycloneIVPLL(speedgrade="-8") self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) pll.create_clkout( self.cd_sys2x_ps, 2 * sys_clk_freq, phase=270) # Ideally 90° but needs to be increased. else: pll.create_clkout( self.cd_sys_ps, sys_clk_freq, phase=180) # Ideally 90° but needs to be increased. # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
def __init__(self, platform, sys_clk_freq, with_usb_pll=False): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # Clk / Rst clk25 = platform.request("clk25") rst = platform.request("rst") # PLL self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(rst) pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) # USB PLL if with_usb_pll: self.submodules.usb_pll = usb_pll = ECP5PLL() usb_pll.register_clkin(clk25, 25e6) self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain() usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0) usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # Prevent ESP32 from resetting FPGA self.comb += platform.request("wifi_gpio0").eq(1)
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # Clk / Rst clk32 = platform.request("clk32") # PLL self.submodules.pll = pll = S6PLL(speedgrade=-1) pll.register_clkin(clk32, 32e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=90) else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi5x = ClockDomain() # # # # Clk / Rst clk32 = platform.request("clk32") # PLL self.submodules.pll = pll = S6PLL(speedgrade=-1) self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk32, 32e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=90) else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) #platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. pll.create_clkout(self.cd_hdmi, 1 * 40e6) pll.create_clkout(self.cd_hdmi5x, 5 * 40e6) # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
def __init__(self, platform, sys_clk_freq, with_usb_pll=False, with_rst=True): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain() # # # # Clk / Rst clk25 = platform.request("clk25") rst_n = 1 if not with_rst else platform.request("user_btn_n", 0) # PLL self.submodules.pll = pll = ECP5PLL() pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n) # USB PLL if with_usb_pll: self.submodules.usb_pll = usb_pll = ECP5PLL() usb_pll.register_clkin(clk25, 25e6) self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain() usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0) usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) # # # # Clk/Rst clk100 = platform.request("clk100") rst_n = platform.request("user_btn_n") # Power On Reset por_count = Signal(16, reset=2**16 - 1) por_done = Signal() self.comb += self.cd_por.clk.eq(ClockSignal()) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) # PLL self.submodules.pll = pll = iCE40PLL() self.comb += pll.reset.eq( rst_n ) # FIXME: Add proper iCE40PLL reset support and add back | self.rst. pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False) self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked) platform.add_period_constraint(self.cd_sys.clk, 1e9 / sys_clk_freq) # SDRAM clock self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys"))
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) self.clock_domains.cd_vga = ClockDomain(reset_less=True) # # # # Clk / Rst clk50 = platform.request("clk50") # PLL self.submodules.pll = pll = CycloneVPLL(speedgrade="-I7") self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90) else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) pll.create_clkout(self.cd_vga, 40e6) # SDRAM clock if with_sdram: sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1", with_led_chaser=True, **kwargs): platform = tec0117.Platform() # Disable Integrated ROM. kwargs["integrated_rom_size"] = 0 # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on TEC0117", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- from litespi.modules import W74M64FV from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=W74M64FV(Codes.READ_1_1_4), with_master=False) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( origin = self.bus.regions["spiflash"].origin + bios_flash_offset, size = 32*kB, linker = True) ) self.cpu.set_reset_address(self.bus.regions["rom"].origin) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: class SDRAMPads: def __init__(self): self.clk = platform.request("O_sdram_clk") self.cke = platform.request("O_sdram_cke") self.cs_n = platform.request("O_sdram_cs_n") self.cas_n = platform.request("O_sdram_cas_n") self.ras_n = platform.request("O_sdram_ras_n") self.we_n = platform.request("O_sdram_wen_n") self.dm = platform.request("O_sdram_dqm") self.a = platform.request("O_sdram_addr") self.ba = platform.request("O_sdram_ba") self.dq = platform.request("IO_sdram_dq") sdram_pads = SDRAMPads() sdram_clk = ClockSignal("sys2x" if sdram_rate == "1:2" else "sys") # FIXME: use phase shift from PLL. self.specials += DDROutput(0, 1, sdram_pads.clk, sdram_clk) sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. l2_cache_size = 128, ) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain() self.clock_domains.cd_por = ClockDomain() # # # # Clk / Rst clk25 = platform.request("clk25") platform.add_period_constraint(clk25, 1e9/25e6) #if sys_clk_freq == 25e6: # self.comb += self.cd_sys.clk.eq(clk25) #else: if True: # PLL self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD") pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) #pll.create_clkout_90(self.cd_sys_ps, sys_clk_freq) platform.add_period_constraint(self.cd_sys.clk, sys_clk_freq) #platform.add_period_constraint(self.cd_sys_ps.clk, sys_clk_freq) self.specials += DDROutput(0, 1, platform.request("sdram_clock"), self.cd_sys.clk) # Power On Reset por_cycles = 4096 por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1) self.comb += self.cd_por.clk.eq(self.cd_sys.clk) platform.add_period_constraint(self.cd_por.clk, 1e9/sys_clk_freq) self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1)) #self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n) self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0) | ~pll.locked)
def __init__(self, sys_clk_freq=int(50e6), revision="revd", sdram_rate="1:2", mister_sdram=None, with_led_chaser=True, with_video_terminal=False, **kwargs): platform = terasic_sockit.Platform(revision) # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "jtag_uart" # Defaults to JTAG-UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on the Terasic SoCKit", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate, with_video_terminal=with_video_terminal) # SDR SDRAM -------------------------------------------------------------------------------- if mister_sdram is not None: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_mod = { "xs_v22": W9825G6KH6, "xs_v24": AS4C32M16 }[mister_sdram] self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=sdrphy_mod(sys_clk_freq, sdram_rate), l2_cache_size=kwargs.get("l2_size", 8192)) # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: vga_pads = platform.request("vga") self.comb += [vga_pads.sync_n.eq(0), vga_pads.blank_n.eq(1)] self.specials += DDROutput(i1=1, i2=0, o=vga_pads.clk, clk=ClockSignal("vga")) self.submodules.videophy = VideoVGAPHY(vga_pads, clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_rst=True, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # Clk / Rst if not use_internal_osc: clk = platform.request("clk25") clk_freq = 25e6 else: clk = Signal() div = 5 self.specials += Instance("OSCG", p_DIV=div, o_OSC=clk) clk_freq = 310e6 / div rst_n = 1 if not with_rst else platform.request("user_btn_n", 0) # PLL self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk, clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) pll.create_clkout( self.cd_sys2x_ps, 2 * sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout( self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. # USB PLL if with_usb_pll: self.submodules.usb_pll = usb_pll = ECP5PLL() self.comb += usb_pll.reset.eq(~rst_n | self.rst) usb_pll.register_clkin(clk, clk_freq) self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain() usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0) usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0) # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1", with_led_chaser=True, **kwargs): platform = tec0117.Platform() # Put BIOS in SPIFlash to save BlockRAMs. kwargs["integrated_rom_size"] = 0 kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on TEC0117", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="4x", dummy_cycles=6) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( origin = self.mem_map["spiflash"] + bios_flash_offset, size = 64*kB, linker = True) ) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: class SDRAMPads: def __init__(self): self.clk = platform.request("O_sdram_clk") self.cke = platform.request("O_sdram_cke") self.cs_n = platform.request("O_sdram_cs_n") self.cas_n = platform.request("O_sdram_cas_n") self.ras_n = platform.request("O_sdram_ras_n") self.we_n = platform.request("O_sdram_wen_n") self.dm = platform.request("O_sdram_dqm") self.a = platform.request("O_sdram_addr") self.ba = platform.request("O_sdram_ba") self.dq = platform.request("IO_sdram_dq") sdram_pads = SDRAMPads() sdram_clk = ClockSignal("sys2x" if sdram_rate == "1:2" else "sys") # FIXME: use phase shift from PLL. self.specials += DDROutput(0, 1, sdram_pads.clk, sdram_clk) sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. l2_cache_size = 128, ) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, pads, clock_domain="sys", pn_swap=[]): self.sink = sink = stream.Endpoint(video_data_layout) # # # # Determine driven polarities: # - p only for True/Pseudo Differential. # - p and n for Fake Differential. drive_pols = [] for pol in ["p", "n"]: if hasattr(pads, f"clk_{pol}"): drive_pols.append(pol) # Always ack Sink, no backpressure. self.comb += sink.ready.eq(1) # Clocking + Pseudo Differential Signaling. for pol in drive_pols: self.specials += DDROutput( i1={ "p": 1, "n": 0 }[pol], i2={ "p": 0, "n": 1 }[pol], o=getattr(pads, f"clk_{pol}"), clk=ClockSignal(clock_domain), ) # Encode/Serialize Datas. for pol in drive_pols: for color in ["r", "g", "b"]: # TMDS Encoding. encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder()) setattr(self.submodules, f"{color}_encoder", encoder) self.comb += encoder.d.eq(getattr(sink, color)) self.comb += encoder.c.eq( Cat(sink.hsync, sink.vsync) if color == "r" else 0) self.comb += encoder.de.eq(sink.de) # 10:1 Serialization + Pseudo Differential Signaling. c2d = {"r": 0, "g": 1, "b": 2} data_i = encoder.out if color not in pn_swap else ~encoder.out data_o = getattr(pads, f"data{c2d[color]}_{pol}") serializer = VideoHDMI10to1Serializer( data_i={ "p": data_i, "n": ~data_i }[pol], data_o=data_o, clock_domain=clock_domain, ) setattr(self.submodules, f"{color}_serializer", serializer)
def __init__(self, platform, sys_clk_freq, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # Clk / Rst clk25 = platform.request("clk25") rst = platform.request("rst") # PLL self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(rst | self.rst) pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # USB PLL if with_usb_pll: self.submodules.usb_pll = usb_pll = ECP5PLL() self.comb += usb_pll.reset.eq(rst | self.rst) usb_pll.register_clkin(clk25, 25e6) self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain() usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0) usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0) # Video PLL if with_video_pll: self.submodules.video_pll = video_pll = ECP5PLL() self.comb += video_pll.reset.eq(rst | self.rst) video_pll.register_clkin(clk25, 25e6) self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi5x = ClockDomain() video_pll.create_clkout(self.cd_hdmi, 25e6, margin=0) video_pll.create_clkout(self.cd_hdmi5x, 125e6, margin=0) # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) # Prevent ESP32 from resetting FPGA self.comb += platform.request("wifi_gpio0").eq(1)
def __init__(self, platform, clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # self.submodules.pll = pll = S6PLL(speedgrade=-1) pll.register_clkin(platform.request("clk32"), 32e6) pll.create_clkout(self.cd_sys, clk_freq) pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) if with_ethernet: self.clock_domains.cd_eth = ClockDomain() if with_vga: self.clock_domains.cd_vga = ClockDomain(reset_less=True) # # # # Clk / Rst clk50 = platform.request("clk50") # PLL self.submodules.pll = pll = CycloneVPLL(speedgrade="-C8") self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) # theoretically 90 degrees, but increase to relax timing pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=180) else: # for 105 MHz: 10; 95 MHz: 15; 85MHz: 30 work pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=10) if with_ethernet: pll.create_clkout(self.cd_eth, 25e6) if with_vga: pll.create_clkout(self.cd_vga, 40e6) # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # clk25 = platform.request("clk25") self.submodules.pll = pll = S6PLL(speedgrade=-2) self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # Clk / Rst clk50 = platform.request("clk50") # PLL self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6") pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_video_terminal=False): self.sdram_rate = sdram_rate self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if with_video_terminal: self.clock_domains.cd_vga = ClockDomain(reset_less=True) if with_sdram: if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # Clk / Rst clk50 = platform.request("clk50") # PLL self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6") self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if with_video_terminal: pll.create_clkout(self.cd_vga, 65e6) if with_sdram: if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) pll.create_clkout( self.cd_sys2x_ps, 2 * sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock if with_sdram: sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # Clk / Rst clk8 = platform.request("clk8") # PLL self.submodules.pll = pll = ECP5PLL() pll.register_clkin(clk8, 8e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, data_i, data_o, clock_domain): # Clock Domain Crossing. self.submodules.cdc = stream.ClockDomainCrossing([("data", 10)], cd_from=clock_domain, cd_to=clock_domain + "5x") self.comb += self.cdc.sink.valid.eq(1) self.comb += self.cdc.sink.data.eq(data_i) # 10:2 Gearbox. self.submodules.gearbox = ClockDomainsRenamer(clock_domain + "5x")(stream.Gearbox(i_dw=10, o_dw=2, msb_first=False)) self.comb += self.cdc.source.connect(self.gearbox.sink) # 2:1 Output DDR. self.comb += self.gearbox.source.ready.eq(1) self.specials += DDROutput( clk = ClockSignal(clock_domain + "5x"), i1 = self.gearbox.source.data[0], i2 = self.gearbox.source.data[1], o = data_o, )
def __init__(self, clock_pads, pads, with_hw_init_reset, tx_delay=2e-9): self._reset = CSRStorage() # # # self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) # RX self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx) # TX tx_delay_taps = int(tx_delay / 25e-12) # 25ps per tap assert tx_delay_taps < 128 eth_tx_clk_o = Signal() self.specials += [ DDROutput(clk=ClockSignal("eth_tx"), i1=1, i2=0, o=eth_tx_clk_o), Instance("DELAYF", p_DEL_MODE="SCLK_ALIGNED", p_DEL_VALUE="DELAY{}".format(tx_delay_taps), i_LOADN=1, i_MOVE=0, i_DIRECTION=0, i_A=eth_tx_clk_o, o_Z=clock_pads.tx) ] # Reset self.reset = reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: self.comb += reset.eq(self._reset.storage) if hasattr(pads, "rst_n"): self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), AsyncResetSynchronizer(self.cd_eth_rx, reset), ]
def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) #self.clock_domains.cd_sys2x = ClockDomain() #self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) # PLL self.submodules.pll = pll = S6PLL(speedgrade=-2) self.comb += pll.reset.eq(~platform.request("cpu_reset") | ~platform.request("cclk")) pll.register_clkin(platform.request("clk50"), 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) #pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) #pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0): self._reset = CSRStorage() # # # self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() # RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk. self.specials += Instance("BUFG", i_I = clock_pads.rx, o_O = ClockSignal("eth_rx"), ) # TX clock: GMII: Drive clock_pads.gtx, clock_pads.tx unused. # MII : Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx. self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx")) eth_tx_clk = Signal() self.comb += [ If(mii_mode, eth_tx_clk.eq(clock_pads.tx) ).Else( eth_tx_clk.eq(clock_pads.rx) ) ] self.specials += Instance("BUFG", i_I = eth_tx_clk, o_O = ClockSignal("eth_tx"), ) # Reset self.reset = reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: self.comb += reset.eq(self._reset.storage) if hasattr(pads, "rst_n"): self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), AsyncResetSynchronizer(self.cd_eth_rx, reset), ]
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0): self._reset = CSRStorage() # # # self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() # RX : Let the synthesis tool insert the appropriate clock buffer self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx) # TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused # MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx")) if isinstance(mii_mode, int) and (mii_mode == 0): self.specials += Instance( "BUFG", i_I=self.cd_eth_rx.clk, o_O=self.cd_eth_tx.clk, ) else: # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer? self.specials += Instance( "BUFGMUX", i_I0=self.cd_eth_rx.clk, i_I1=clock_pads.tx, i_S=mii_mode, o_O=self.cd_eth_tx.clk, ) reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: self.comb += reset.eq(self._reset.storage) self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), AsyncResetSynchronizer(self.cd_eth_rx, reset), ]