def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
BaseSoC.__init__(self, platform, spiflash, **kwargs)
platform.add_extension(i2c_pmod_d)
# i2c master
i2c_pads = platform.request("i2c_pmodd", 0)
self.submodules.i2c0 = I2CMaster(i2c_pads)
self.add_csr("i2c0")
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = zcu104.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
cmd_latency = 1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MTA4ATF51264HZ(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
self.submodules.i2c = I2CMaster(platform.request("i2c"))
self.add_csr("i2c")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
with_spi_flash=False,
**kwargs):
platform = mnt_rkx7.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on MNT-RKX7",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=IS43TR16512B(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192),
)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
rate="1:1",
with_master=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
platform.add_platform_command(
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {{main_ethphy_eth_rx_clk_ibuf}}]"
)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# I2C --------------------------------------------------------------------------------------
self.submodules.i2c = I2CMaster(platform.request("i2c"))
def __init__(self):
SimSoC.__init__(self, cpu_type=None)
self.platform.add_source("I2C_slave.v")
# For making sure csr registers are read back correctly
self.status_test = CSRStatus(8)
self.comb += self.status_test.status.eq(0xDE)
# For testing bit-banging I2C
self.submodules.i2c_master = m = I2CMaster()
self.add_csr('i2c_master')
# Hardwire SDA line to High!!!
self.comb += m.pads.sda.eq(1)
def __init__(self, **kwargs):
min_rom = 0x9000
if kwargs["integrated_rom_size"] < min_rom:
kwargs["integrated_rom_size"] = min_rom
super().__init__(**kwargs)
if self.args.sim:
return
# SPD EEPROM I2C ---------------------------------------------------------------------------
self.submodules.i2c = I2CMaster(self.platform.request("i2c"))
self.add_csr("i2c")
# ZynqUS+ PS -------------------------------------------------------------------------------
self.submodules.ps = ZynqUSPS()
# Configure PS->PL AXI
# AXI(32) -> AXILite(32) -> WishBone(32) -> SoC Interconnect
axi_ps = self.ps.add_axi_gp_fpd_master(data_width=32)
axi_lite_ps = axi.AXILiteInterface(data_width=32, address_width=40)
self.submodules += axi.AXI2AXILite(axi_ps, axi_lite_ps)
# Use M_AXI_HPM0_FPD base address thaht will fit our whole address space (0x0004_0000_0000)
base_address = None
for base, size in self.ps.PS_MEMORY_MAP['gp_fpd_master'][0]:
if size >= 2**30 - 1:
base_address = base
break
assert base_address is not None
def chunks(lst, n):
for i in range(0, len(lst), n):
yield lst[i:i + n]
addr_str = '_'.join(chunks('{:012x}'.format(base_address), 4))
self.logger.info("Connecting PS AXI master from PS address {}.".format(
colorer('0x' + addr_str)))
wb_ps = wishbone.Interface(
adr_width=40 -
2) # AXILite2Wishbone requires the same address widths
self.submodules += axi.AXILite2Wishbone(axi_lite_ps,
wb_ps,
base_address=base_address)
# silently ignores address bits above 30
self.bus.add_master(name='ps_axi', master=wb_ps)
def __init__(self, p, soc):
# -------------------------------------------------------
# Si570 Pmod
# -------------------------------------------------------
# Connect Si570 (sample clk) to I2C master
p.add_extension([("SI570_I2C", 0, Subsignal("oe", Pins("pmodb:5")),
Subsignal("scl", Pins("pmodb:6")),
Subsignal("sda",
Pins("pmodb:7")), IOStandard("LVCMOS33"))])
si570_pads = p.request("SI570_I2C")
# soc.add_emio_i2c(si570_pads, 0) # PS I2C0
self.submodules.i2c = I2CMaster(si570_pads) # Litex bit-bang
self.si570_oe = CSRStorage(1, reset=1, name="si570_oe")
self.comb += si570_pads.oe.eq(self.si570_oe.storage)
def __init__(self, platform, pads, disable_i2c=False):
pad_count = len(pads)
if not disable_i2c:
self.i2c_master = I2CMaster(pads)
self.gpio = GPIOBidirectional(pads, disable_i2c)
def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
with_led_chaser = True,
with_video_terminal = True,
with_video_framebuffer = False,
**kwargs):
platform = ecp5_vip.Platform(toolchain=toolchain)
#bios_flash_offset = 0x400000
# Set CPU variant / reset address
#kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
kwargs["integrated_rom_size"] = 0x10000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ECP5 Evaluation Board",
#integrated_main_ram_size = 0x4000,
#integrated_main_ram_size = 0,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"), # Not entirely MT41J64M16 but similar and works(c)
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
pads = platform.request("hdmi")
self.submodules.videophy = VideoVGAPHY(pads, clock_domain="hdmi")
self.submodules.videoi2c = I2CMaster(pads)
# # 1920x1080@60Hz
# pixel_clock_hz = 160e6
# framerate_hz = 60
# pixels_horizontal = 2200
# pixels_vertical = 1125
# 800x600@60Hz
pixel_clock_hz = 40e6
framerate_hz = 60
pixels_horizontal = 1056
pixels_vertical = 628
# # 1920x1080@30Hz
# pixel_clock_hz = 80e6
# framerate_hz = 30
# pixels_horizontal = 2640
# pixels_vertical = 1125
self.videoi2c.add_init(addr=0x3B, init=[
(0xc7, 0x00), # HDMI configuration
(0xc7, 0x00), # Write twice, the first transfer fails for some reason
(0x1e, 0x00), # Power up transmitter
(0x08, 0x60), # Input Bus/Pixel Repetition (default)
(0x00, int((pixel_clock_hz/1e4) %256)), # Pixel clock in MHz * 100
(0x01, int((pixel_clock_hz/1e4)//256)), #
(0x02, int((framerate_hz*100) %256)), # Framerate * 100
(0x03, int((framerate_hz*100)//256)), #
(0x04, int((pixels_horizontal) %256)), # Pixels horizontal
(0x05, int((pixels_horizontal)//256)), #
(0x06, int((pixels_vertical) %256)), # Pixels vertical
(0x07, int((pixels_vertical)//256)), #
(0x1a, 0x00) # end
])
if with_video_terminal:
#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
#self.add_video_terminal(phy=self.videophy, timings="1920x1080@30Hz", clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
if with_video_framebuffer:
#self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
with_video_terminal=False,
with_video_framebuffer=False,
with_led_chaser=True,
with_pmod_gpio=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# HDMI -------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
# PHY + TP410 I2C initialization.
hdmi_pads = platform.request("hdmi")
self.submodules.videophy = VideoDVIPHY(hdmi_pads,
clock_domain="init")
self.submodules.videoi2c = I2CMaster(hdmi_pads)
self.videoi2c.add_init(
addr=0x38,
init=[(0x08, 0x35
) # CTL_1_MODE: Normal operation, 24-bit, HSYNC/VSYNC.
])
# Video Terminal/Framebuffer.
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = Platform()
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_variant="standard+debug",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# CRG --------------------------------------------------------------------------------------
self.submodules.uartbridge = UARTWishboneBridge(
platform.request("serial2"), int(sys_clk_freq), baudrate=115200)
self.add_wb_master(self.uartbridge.wishbone)
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus,
0x10)
tp_list = Cat(platform.request("TP1"), platform.request("TP2"),
platform.request("TP3"), platform.request("TP4"),
platform.request("TP5"), platform.request("TP6"),
platform.request("TP7"), platform.request("TP8"))
print(
"===================================================================="
)
print(tp_list)
print(
"===================================================================="
)
self.submodules.tp = GPIOTristate(tp_list)
self.add_csr("tp")
j1_35_pads = platform.request("J1_35")
print(
"===================================================================="
)
print(j1_35_pads)
print(
"===================================================================="
)
self.submodules.j1_35 = GPIOTristate(j1_35_pads)
self.add_csr("j1_35")
self.submodules.j1_34 = GPIOTristate(platform.request("J1_34"))
self.add_csr("j1_34")
self.submodules.j2_14 = GPIOTristate(platform.request("J2_14"))
self.add_csr("j2_14")
self.submodules.j2_16 = GPIOTristate(platform.request("J2_16"))
self.add_csr("j2_16")
self.submodules.led = GPIOOut(platform.request("rgb_led").raw_bits())
self.add_csr("led")
self.submodules.usba = GPIOTristate(
platform.request("usb_a").raw_bits())
self.add_csr("usba")
self.submodules.usbmicro = GPIOTristate(
platform.request("usb_micro").raw_bits())
self.add_csr("usbmicro")
self.submodules.clk_i2c = I2CMaster(pads=platform.request("clk_i2c"))
self.add_csr("clk_i2c")
self.submodules.pcie_ctrl = GPIOTristate(
platform.request("pcie_ctrl").raw_bits())
self.add_csr("pcie_ctrl")
self.submodules.spi_flash = spi_flash.SpiFlashDualQuad(
platform.request("spiflash4x"),
with_bitbang=True,
endianness="little")
self.spi_flash.add_clk_primitive(platform.device)
self.add_csr("spi_flash")
self.submodules.ethernet = Serdes(platform)
def add_i2c(self):
self.submodules.i2c0 = I2CMaster(self.platform.request("i2c", 0))
self.add_csr("i2c0")
def __init__(self,
device="85F",
sys_clk_freq=int(75e6),
with_ethernet=False,
with_etherbone=False,
with_video_terminal=False,
with_video_framebuffer=False,
with_led_chaser=True,
**kwargs):
platform = ecpix5.Platform(device=device, toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ECPIX-5",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# HDMI -------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
# PHY + IT6613 I2C initialization.
hdmi_pads = platform.request("hdmi")
self.submodules.videophy = VideoDVIPHY(hdmi_pads,
clock_domain="init")
self.submodules.videoi2c = I2CMaster(hdmi_pads)
# I2C initialization adapted from https://github.com/ultraembedded/ecpix-5
# Copyright (c) 2020 https://github.com/ultraembedded
# Adapted from C to Python.
REG_TX_SW_RST = 0x04
B_ENTEST = (1 << 7)
B_REF_RST = (1 << 5)
B_AREF_RST = (1 << 4)
B_VID_RST = (1 << 3)
B_AUD_RST = (1 << 2)
B_HDMI_RST = (1 << 1)
B_HDCP_RST = (1 << 0)
REG_TX_AFE_DRV_CTRL = 0x61
B_AFE_DRV_PWD = (1 << 5)
B_AFE_DRV_RST = (1 << 4)
B_AFE_DRV_PDRXDET = (1 << 2)
B_AFE_DRV_TERMON = (1 << 1)
B_AFE_DRV_ENCAL = (1 << 0)
REG_TX_AFE_XP_CTRL = 0x62
B_AFE_XP_GAINBIT = (1 << 7)
B_AFE_XP_PWDPLL = (1 << 6)
B_AFE_XP_ENI = (1 << 5)
B_AFE_XP_ER0 = (1 << 4)
B_AFE_XP_RESETB = (1 << 3)
B_AFE_XP_PWDI = (1 << 2)
B_AFE_XP_DEI = (1 << 1)
B_AFE_XP_DER = (1 << 0)
REG_TX_AFE_ISW_CTRL = 0x63
B_AFE_RTERM_SEL = (1 << 7)
B_AFE_IP_BYPASS = (1 << 6)
M_AFE_DRV_ISW = (7 << 3)
O_AFE_DRV_ISW = 3
B_AFE_DRV_ISWK = 7
REG_TX_AFE_IP_CTRL = 0x64
B_AFE_IP_GAINBIT = (1 << 7)
B_AFE_IP_PWDPLL = (1 << 6)
M_AFE_IP_CKSEL = (3 << 4)
O_AFE_IP_CKSEL = 4
B_AFE_IP_ER0 = (1 << 3)
B_AFE_IP_RESETB = (1 << 2)
B_AFE_IP_ENC = (1 << 1)
B_AFE_IP_EC1 = (1 << 0)
REG_TX_HDMI_MODE = 0xC0
B_TX_HDMI_MODE = 1
B_TX_DVI_MODE = 0
REG_TX_GCP = 0xC1
B_CLR_AVMUTE = 0
B_SET_AVMUTE = 1
B_TX_SETAVMUTE = (1 << 0)
B_BLUE_SCR_MUTE = (1 << 1)
B_NODEF_PHASE = (1 << 2)
B_PHASE_RESYNC = (1 << 3)
self.videoi2c.add_init(
addr=0x4c,
init=[
# Reset.
(REG_TX_SW_RST, B_REF_RST | B_VID_RST | B_AUD_RST
| B_AREF_RST | B_HDCP_RST),
(REG_TX_SW_RST, 0),
# Select DVI Mode.
(REG_TX_HDMI_MODE, B_TX_DVI_MODE),
# Configure Clks.
(REG_TX_SW_RST, B_AUD_RST | B_AREF_RST | B_HDCP_RST),
(REG_TX_AFE_DRV_CTRL, B_AFE_DRV_RST),
(REG_TX_AFE_XP_CTRL, 0x18),
(REG_TX_AFE_ISW_CTRL, 0x10),
(REG_TX_AFE_IP_CTRL, 0x0C),
# Enable Clks.
(REG_TX_AFE_DRV_CTRL, 0),
# Enable Video.
(REG_TX_GCP, 0),
])
# Video Terminal/Framebuffer.
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
leds_pads = []
for i in range(4):
rgb_led_pads = platform.request("rgb_led", i)
self.comb += [getattr(rgb_led_pads, n).eq(1)
for n in "gb"] # Disable Green/Blue Leds.
leds_pads += [getattr(rgb_led_pads, n) for n in "r"]
self.submodules.leds = LedChaser(pads=Cat(leds_pads),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_led_chaser=True,
with_pcie=False,
with_sata=False,
**kwargs):
platform = stlv7325.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on STLV7325",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks", 0),
pads=self.platform.request("eth", 0),
clk_freq=self.clk_freq)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# TODO verify / test
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk=sata_refclk,
pads=platform.request(
"sata", 0),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led_n"),
sys_clk_freq=sys_clk_freq)
# I2C --------------------------------------------------------------------------------------
self.submodules.i2c = I2CMaster(platform.request("i2c"))
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_etherbone=False,
with_rts_reset=False,
with_led_chaser=True,
spd_dump=None,
**kwargs):
platform = berkeleylab_marble.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Berkeley-Lab Marble",
**kwargs)
# CRG, resettable over USB serial RTS signal -----------------------------------------------
resets = []
if with_rts_reset:
ser_pads = platform.lookup_request('serial')
resets.append(ser_pads.rts)
self.submodules.crg = _CRG(platform, sys_clk_freq, resets)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
if spd_dump is not None:
ram_spd = parse_spd_hexdump(spd_dump)
ram_module = SDRAMModule.from_spd_data(ram_spd, sys_clk_freq)
print('DDR3: loaded config from', spd_dump)
else:
ram_module = MT8JTF12864(sys_clk_freq,
"1:4") # KC705 chip, 1 GB
print(
'DDR3: No spd data specified, falling back to MT8JTF12864')
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=ram_module,
# size=0x40000000, # Limit its size to 1 GB
l2_cache_size=kwargs.get("l2_size", 8192),
with_bist=kwargs.get("with_bist", False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
tx_delay=0)
if with_ethernet:
self.add_ethernet(phy=self.ethphy,
dynamic_ip=True,
software_debug=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# System I2C (behing multiplexer) ----------------------------------------------------------
i2c_pads = platform.request('i2c_fpga')
self.submodules.i2c = I2CMaster(i2c_pads)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
platform = de0nano.Platform()
platform.toolchain.additional_qsf_commands = [
'set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"',
]
platform.toolchain.additional_sdc_commands = [
'create_clock -name eth_rx_clk -period 20 [get_ports eth_clocks_ref_clk]',
'create_clock -name eth_rx_clk_virt -period 20',
'derive_clock_uncertainty',
'set CLKAs_max 0.0',
'set CLKAs_min 0.0',
'set CLKAd_max 1.13',
'set CLKAd_min 0.87',
'set tCOa_max 16',
'set tCOa_min 1',
'set BDa_max 1.13',
'set BDa_min 0.87',
'set_input_delay -clock eth_rx_clk_virt -max [expr $CLKAs_max + $tCOa_max + $BDa_max - $CLKAd_min] [get_ports {eth_rx_data[*] eth_crs_dv}]',
'set_input_delay -clock eth_rx_clk_virt -min [expr $CLKAs_min + $tCOa_min + $BDa_min - $CLKAd_max] [get_ports {eth_rx_data[*] eth_crs_dv}]',
]
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE0-Nano",
ident_version=True,
cpu_type="vexriscv_smp",
cpu_variant="linux",
max_sdram_size=0x40000000, # Limit mapped SDRAM to 1GB.
**kwargs)
# Add linker region for OpenSBI
self.add_memory_region("opensbi",
self.mem_map["main_ram"] + 0x00f00000,
0x80000,
type="cached+linker")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# UART -------------------------------------------------------------------------------------
_uart_jp_ios = [("uart", 0,
Subsignal("tx", Pins("JP1:34"),
IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("JP1:32"),
IOStandard("3.3-V LVTTL")))]
self.platform.add_extension(_uart_jp_ios)
self.add_uart(name="uart", baudrate=921600, fifo_depth=1024)
# Leds -------------------------------------------------------------------------------------
led_pads = platform.request_all("user_led")
self.submodules.leds = GPIOOut(led_pads)
self.add_constant("LEDS_NGPIO", len(led_pads))
# Keys -------------------------------------------------------------------------------------
switches_pads = self.platform.request_all("key")
self.submodules.switches = GPIOIn(pads=switches_pads, with_irq=True)
self.irq.add("switches", use_loc_if_exists=True)
self.add_constant("SWITCHES_NGPIO", len(switches_pads))
# RMII Ethernet ----------------------------------------------------------------------------
_ethernet_jp_ios = [
(
"eth_clocks",
0,
Subsignal("ref_clk", Pins("JP2:34")),
IOStandard("3.3-V LVTTL"),
),
(
"eth",
0,
#Subsignal("rst_n", Pins("")),
Subsignal("rx_data", Pins("JP2:36 JP2:35")),
Subsignal("crs_dv", Pins("JP2:33")),
Subsignal("tx_en", Pins("JP2:38")),
Subsignal("tx_data", Pins("JP2:37 JP2:40")),
Subsignal("mdc", Pins("JP2:31")),
Subsignal("mdio", Pins("JP2:32")),
#Subsignal("rx_er", Pins("")),
#Subsignal("int_n", Pins("")),
IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_ethernet_jp_ios)
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
refclk_cd=None,
)
self.add_ethernet(phy=self.ethphy, nrxslots=4, ntxslots=2)
# SD Card ----------------------------------------------------------------------------------
_sdcard_jp_ios = [
(
"sdcard",
0,
Subsignal("data", Pins("JP2:14 JP2:24 JP2:22 JP2:20"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("cmd", Pins("JP2:16"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("clk", Pins("JP2:18")),
Subsignal("cd", Pins("JP2:26")),
Misc("FAST_OUTPUT_REGISTER ON"),
IOStandard("3.3-V LVTTL"),
),
]
#_sdcard_jp_ios = [
# ("spisdcard", 0,
# Subsignal("miso", Pins("JP2:14"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("mosi", Pins("JP2:16"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("clk", Pins("JP2:18")),
# Subsignal("cs_n", Pins("JP2:20"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Misc("FAST_OUTPUT_REGISTER ON"),
# IOStandard("3.3-V LVTTL"),
# ),
#]
self.platform.add_extension(_sdcard_jp_ios)
self.add_sdcard()
#self.add_spi_sdcard()
# EPCS ------------------------------------------------------------------------------------
_spi_flash_ios = [
("spiflash", 0, Subsignal("miso", Pins("H2")),
Subsignal("clk", Pins("H1")), Subsignal("cs_n", Pins("D2")),
Subsignal("mosi", Pins("C1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_spi_flash_ios)
self.add_spi_flash(mode="1x", dummy_cycles=8)
# I2C ADXL345 -----------------------------------------------------------------------------
_i2c_ios = [
("i2c_onboard", 0, Subsignal("scl", Pins("F2")),
Subsignal("sda", Pins("F1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_i2c_ios)
self.submodules.i2c0 = I2CMaster(
self.platform.request("i2c_onboard", 0))
adxl_pads = self.platform.request("acc")
self.comb += adxl_pads.cs_n.eq(1)
# ADC -------------------------------------------------------------------------------------
_spi_ios = [("adc128s", 0, Subsignal("cs_n", Pins("A10")),
Subsignal("mosi",
Pins("B10")), Subsignal("clk", Pins("B14")),
Subsignal("miso", Pins("A9")), IOStandard("3.3-V LVTTL"))]
self.platform.add_extension(_spi_ios)
spi_pads = self.platform.request("adc128s")
self.submodules.spi = SPIMaster(spi_pads, 8, self.clk_freq, 1e6)
self.add_csr("spi")
# interrupts ------------------------------------------------------------------------------
#_interrupts_jp_ios = [
# ("interrupt", 0, Pins("JP2:1"), IOStandard("3.3-V LVTTL")),
# ("interrupt", 1, Pins("JP2:26"), IOStandard("3.3-V LVTTL")),
#]
#self.platform.add_extension(_interrupts_jp_ios)
#interrupts_pads = self.platform.request_all("interrupt")
interrupts_pads = adxl_pads.int
self.submodules.interrupts = GPIOIn(interrupts_pads, with_irq=True)
self.irq.add("interrupts", use_loc_if_exists=True)
self.add_constant("INTERRUPTS_NGPIO", len(interrupts_pads))
def __init__(self,
sys_clk_freq=int(75e6),
with_spi_flash=False,
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
eth_ip="192.168.1.50",
with_led_chaser=True,
**kwargs):
platform = efinix_trion_t120_bga576_dev_kit.Platform()
# USBUART PMOD as Serial--------------------------------------------------------------------
platform.add_extension(
efinix_trion_t120_bga576_dev_kit.usb_pmod_io("pmod_e"))
kwargs["uart_name"] = "usb_uart"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=True)
platform.toolchain.excluded_ios.append(
platform.lookup_request("spiflash4x").dq)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# Tristate Test ----------------------------------------------------------------------------
from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
from litex.soc.cores.bitbang import I2CMaster
platform.add_extension([(
"i2c",
0,
Subsignal("sda", Pins("T12")),
Subsignal("scl", Pins("V11")),
IOStandard("3.3_V_LVTTL_/_LVCMOS"),
)])
self.submodules.i2c = I2CMaster(pads=platform.request("i2c"))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
platform=platform,
clock_pads=platform.request("eth_clocks", eth_phy),
pads=platform.request("eth", eth_phy),
with_hw_init_reset=False)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, software_debug=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# FIXME: Avoid this.
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth_clocks").tx)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth_clocks").rx)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").tx_data)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").rx_data)
platform.toolchain.excluded_ios.append(
platform.lookup_request("eth").mdio)
# LPDDR3 SDRAM -----------------------------------------------------------------------------
if not self.integrated_main_ram_size:
# DRAM / PLL Blocks.
# ------------------
dram_pll_refclk = platform.request("dram_pll_refclk")
platform.toolchain.excluded_ios.append(dram_pll_refclk)
self.platform.toolchain.additional_sdc_commands.append(
f"create_clock -period {1e9/50e6} dram_pll_refclk")
from litex.build.efinix import InterfaceWriterBlock, InterfaceWriterXMLBlock
import xml.etree.ElementTree as et
class PLLDRAMBlock(InterfaceWriterBlock):
@staticmethod
def generate():
return """
design.create_block("dram_pll", block_type="PLL")
design.set_property("dram_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
design.gen_pll_ref_clock("dram_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="dram_pll_clkin", ext_refclk_no="0")
design.set_property("dram_pll","LOCKED_PIN","dram_pll_locked", block_type="PLL")
design.set_property("dram_pll","RSTN_PIN","dram_pll_rst_n", block_type="PLL")
design.set_property("dram_pll", {"CLKOUT0_PIN" : "dram_pll_CLKOUT0"}, block_type="PLL")
design.set_property("dram_pll","CLKOUT0_PHASE","0","PLL")
calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
"""
platform.toolchain.ifacewriter.blocks.append(PLLDRAMBlock())
class DRAMXMLBlock(InterfaceWriterXMLBlock):
@staticmethod
def generate(root, namespaces):
# CHECKME: Switch to DDRDesignService?
ddr_info = root.find("efxpt:ddr_info", namespaces)
ddr = et.SubElement(ddr_info,
"efxpt:ddr",
name="ddr_inst1",
ddr_def="DDR_0",
cs_preset_id="173",
cs_mem_type="LPDDR3",
cs_ctrl_width="x32",
cs_dram_width="x32",
cs_dram_density="8G",
cs_speedbin="800",
target0_enable="true",
target1_enable="true",
ctrl_type="none")
gen_pin_target0 = et.SubElement(ddr,
"efxpt:gen_pin_target0")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wdata",
type_name=f"WDATA_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wready",
type_name=f"WREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wid",
type_name=f"WID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bready",
type_name=f"BREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rdata",
type_name=f"RDATA_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aid",
type_name=f"AID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bvalid",
type_name=f"BVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rlast",
type_name=f"RLAST_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_bid",
type_name=f"BID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_asize",
type_name=f"ASIZE_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_atype",
type_name=f"ATYPE_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aburst",
type_name=f"ABURST_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wvalid",
type_name=f"WVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wlast",
type_name=f"WLAST_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aaddr",
type_name=f"AADDR_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rid",
type_name=f"RID_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_avalid",
type_name=f"AVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rvalid",
type_name=f"RVALID_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_alock",
type_name=f"ALOCK_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rready",
type_name=f"RREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_rresp",
type_name=f"RRESP_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_wstrb",
type_name=f"WSTRB_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_aready",
type_name=f"AREADY_0",
is_bus="false")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi0_alen",
type_name=f"ALEN_0",
is_bus="true")
et.SubElement(gen_pin_target0,
"efxpt:pin",
name="axi_clk",
type_name=f"ACLK_0",
is_bus="false",
is_clk="true",
is_clk_invert="false")
gen_pin_target1 = et.SubElement(ddr,
"efxpt:gen_pin_target1")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wdata",
type_name=f"WDATA_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wready",
type_name=f"WREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wid",
type_name=f"WID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bready",
type_name=f"BREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rdata",
type_name=f"RDATA_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aid",
type_name=f"AID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bvalid",
type_name=f"BVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rlast",
type_name=f"RLAST_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_bid",
type_name=f"BID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_asize",
type_name=f"ASIZE_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_atype",
type_name=f"ATYPE_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aburst",
type_name=f"ABURST_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wvalid",
type_name=f"WVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wlast",
type_name=f"WLAST_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aaddr",
type_name=f"AADDR_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rid",
type_name=f"RID_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_avalid",
type_name=f"AVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rvalid",
type_name=f"RVALID_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_alock",
type_name=f"ALOCK_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rready",
type_name=f"RREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_rresp",
type_name=f"RRESP_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_wstrb",
type_name=f"WSTRB_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_aready",
type_name=f"AREADY_1",
is_bus="false")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi1_alen",
type_name=f"ALEN_1",
is_bus="true")
et.SubElement(gen_pin_target1,
"efxpt:pin",
name="axi_clk",
type_name=f"ACLK_1",
is_bus="false",
is_clk="true",
is_clk_invert="false")
gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SEQ_RST",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SCL_IN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SEQ_START",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="RSTN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SDA_IN",
is_bus="false")
et.SubElement(gen_pin_config,
"efxpt:pin",
name="",
type_name="CFG_SDA_OEN",
is_bus="false")
cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga")
et.SubElement(cs_fpga,
"efxpt:param",
name="FPGA_ITERM",
value="120",
value_type="str")
et.SubElement(cs_fpga,
"efxpt:param",
name="FPGA_OTERM",
value="34",
value_type="str")
cs_memory = et.SubElement(ddr, "efxpt:cs_memory")
et.SubElement(cs_memory,
"efxpt:param",
name="RTT_NOM",
value="RZQ/2",
value_type="str")
et.SubElement(cs_memory,
"efxpt:param",
name="MEM_OTERM",
value="40",
value_type="str")
et.SubElement(cs_memory,
"efxpt:param",
name="CL",
value="RL=6/WL=3",
value_type="str")
timing = et.SubElement(ddr, "efxpt:cs_memory_timing")
et.SubElement(timing,
"efxpt:param",
name="tRAS",
value="42.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRC",
value="60.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRP",
value="18.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRCD",
value="18.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tREFI",
value="3.900",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRFC",
value="210.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRTP",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tWTR",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tRRD",
value="10.000",
value_type="float")
et.SubElement(timing,
"efxpt:param",
name="tFAW",
value="50.000",
value_type="float")
cs_control = et.SubElement(ddr, "efxpt:cs_control")
et.SubElement(cs_control,
"efxpt:param",
name="AMAP",
value="ROW-COL_HIGH-BANK-COL_LOW",
value_type="str")
et.SubElement(cs_control,
"efxpt:param",
name="EN_AUTO_PWR_DN",
value="Off",
value_type="str")
et.SubElement(cs_control,
"efxpt:param",
name="EN_AUTO_SELF_REF",
value="No",
value_type="str")
cs_gate_delay = et.SubElement(ddr, "efxpt:cs_gate_delay")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="EN_DLY_OVR",
value="No",
value_type="str")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="GATE_C_DLY",
value="3",
value_type="int")
et.SubElement(cs_gate_delay,
"efxpt:param",
name="GATE_F_DLY",
value="0",
value_type="int")
platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock())
# DRAM Rst.
# ---------
dram_pll_rst_n = platform.add_iface_io("dram_pll_rst_n")
self.comb += dram_pll_rst_n.eq(platform.request("user_btn", 1))
# DRAM AXI-Ports.
# --------------
for n, data_width in {
0: 256, # target0: 256-bit.
1: 128, # target1: 128-bit
}.items():
axi_port = axi.AXIInterface(data_width=data_width,
address_width=28,
id_width=8) # 256MB.
ios = [(
f"axi{n}",
0,
Subsignal("wdata", Pins(data_width)),
Subsignal("wready", Pins(1)),
Subsignal("wid", Pins(8)),
Subsignal("bready", Pins(1)),
Subsignal("rdata", Pins(data_width)),
Subsignal("aid", Pins(8)),
Subsignal("bvalid", Pins(1)),
Subsignal("rlast", Pins(1)),
Subsignal("bid", Pins(8)),
Subsignal("asize", Pins(3)),
Subsignal("atype", Pins(1)),
Subsignal("aburst", Pins(2)),
Subsignal("wvalid", Pins(1)),
Subsignal("aaddr", Pins(32)),
Subsignal("rid", Pins(8)),
Subsignal("avalid", Pins(1)),
Subsignal("rvalid", Pins(1)),
Subsignal("alock", Pins(2)),
Subsignal("rready", Pins(1)),
Subsignal("rresp", Pins(2)),
Subsignal("wstrb", Pins(data_width // 8)),
Subsignal("aready", Pins(1)),
Subsignal("alen", Pins(8)),
Subsignal("wlast", Pins(1)),
)]
io = platform.add_iface_ios(ios)
rw_n = axi_port.ar.valid
self.comb += [
# Pseudo AW/AR Channels.
io.atype.eq(~rw_n),
io.aaddr.eq(Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)),
io.aid.eq(Mux(rw_n, axi_port.ar.id, axi_port.aw.id)),
io.alen.eq(Mux(rw_n, axi_port.ar.len, axi_port.aw.len)),
io.asize.eq(Mux(rw_n, axi_port.ar.size, axi_port.aw.size)),
io.aburst.eq(
Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)),
io.alock.eq(Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)),
io.avalid.eq(
Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)),
axi_port.aw.ready.eq(~rw_n & io.aready),
axi_port.ar.ready.eq(rw_n & io.aready),
# R Channel.
axi_port.r.id.eq(io.rid),
axi_port.r.data.eq(io.rdata),
axi_port.r.last.eq(io.rlast),
axi_port.r.resp.eq(io.rresp),
axi_port.r.valid.eq(io.rvalid),
io.rready.eq(axi_port.r.ready),
# W Channel.
io.wid.eq(axi_port.w.id),
io.wstrb.eq(axi_port.w.strb),
io.wdata.eq(axi_port.w.data),
io.wlast.eq(axi_port.w.last),
io.wvalid.eq(axi_port.w.valid),
axi_port.w.ready.eq(io.wready),
# B Channel.
axi_port.b.id.eq(io.bid),
axi_port.b.valid.eq(io.bvalid),
io.bready.eq(axi_port.b.ready),
]
# Connect AXI interface to the main bus of the SoC.
axi_lite_port = axi.AXILiteInterface(data_width=data_width,
address_width=28)
self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
self.bus.add_slave(f"target{n}", axi_lite_port,
SoCRegion(origin=0x4000_0000 +
0x1000_0000 * n,
size=0x1000_0000)) # 256MB.
# Use DRAM's target0 port as Main Ram -----------------------------------------------------
self.bus.add_region(
"main_ram",
SoCRegion(
origin=0x4000_0000,
size=0x1000_0000, # 256MB.
linker=True))
def __init__(self,
*,
sys_clk_freq=int(100e6),
iodelay_clk_freq=200e6,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_hyperram=False,
with_sdcard=False,
with_jtagbone=True,
with_uartbone=False,
with_led_chaser=True,
eth_reset_time,
**kwargs):
platform = datacenter_ddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on data center test board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
iodelay_clk_freq=iodelay_clk_freq)
# DDR4 SDRAM RDIMM -------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = A7DDRPHY(
platform.request("ddr4"),
memtype="DDR4",
iodelay_clk_freq=iodelay_clk_freq,
sys_clk_freq=sys_clk_freq,
is_rdimm=True,
)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=256,
size=0x40000000,
)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.bus.add_slave("hyperram",
slave=self.hyperram.bus,
region=SoCRegion(origin=0x20000000,
size=8 * 1024 * 1024))
# SD Card ----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0.8e-9,
hw_reset_cycles=math.ceil(
float(eth_reset_time) * self.sys_clk_freq))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# System I2C (behing multiplexer) ----------------------------------------------------------
i2c_pads = platform.request('i2c')
self.submodules.i2c = I2CMaster(i2c_pads)
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
# Board Revision ---------------------------------------------------------------------------
revision = kwargs.get("revision", "0.2")
device = kwargs.get("device", "25F")
platform = orangecrab.Platform(revision=revision,
device=device,
toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
#platform.add_extension(orangecrab.feather_serial)
# USB hardware Abstract Control Model.
kwargs['uart_name'] = "usb_acm"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
csr_data_width=32,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = crg = CRG(platform,
sys_clk_freq,
with_usb_pll=True)
# DDR3 SDRAM -------------------------------------------------------------------------------
if 1:
if not self.integrated_main_ram_size:
available_sdram_modules = {
'MT41K64M16': MT41K64M16,
'MT41K128M16': MT41K128M16,
'MT41K256M16': MT41K256M16
}
sdram_module = available_sdram_modules.get(
kwargs.get("sdram_device", "MT41K64M16"))
ddr_pads = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(ddr_pads,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY")
self.comb += crg.stop.eq(self.ddrphy.init.stop)
self.comb += crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=sdram_module(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Virtual power pins - suggested to reduce SSO noise
self.comb += ddr_pads.vccio.eq(0b111111)
self.comb += ddr_pads.gnd.eq(0)
# Add extra pin definitions
platform.add_extension(extras)
# RGB LED
led = platform.request("rgb_led", 0)
self.submodules.gpio_led = GPIOTristate(Cat(led.r, led.g, led.b))
# i2c
self.submodules.i2c = I2CMaster(platform.request("i2c"))
# SDR processor
self.submodules.sdr = sdr(platform.request("ad9203"),
platform.request("pdm_out"))
platform.add_source_dir('vsrc')
# Controllable Self Reset
reset_code = Signal(32, reset=0)
self.submodules.self_reset = GPIOOut(reset_code)
self.comb += platform.request("rst_n").eq(reset_code != 0xAA550001)
self.submodules.button = GPIOIn(platform.request("usr_btn"))
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads,
dummy=6,
endianness="little")
self.lxspi.add_clk_primitive(platform.device)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=16 * 1024 * 1024)
# Add GIT repo to the firmware
git_rev_cmd = subprocess.Popen(["git", "rev-parse", "--short", "HEAD"],
stdout=subprocess.PIPE,
stderr=subprocess.PIPE)
(git_stdout, _) = git_rev_cmd.communicate()
self.add_constant('REPO_GIT_SHA1',
git_stdout.decode('ascii').strip('\n'))
def __init__(self,
sys_clk_freq=int(75e6),
with_spi_flash=False,
with_ethernet=False,
with_etherbone=False,
with_video_terminal=False,
with_lcd=False,
with_ws2812=False,
**kwargs):
platform = litex_acorn_baseboard.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on LiteX M2 Baseboard",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_video_pll=with_video_terminal)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"),
clock_domain="hdmi",
pn_swap=["g", "b"])
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
# LCD --------------------------------------------------------------------------------------
if with_lcd:
self.submodules.i2c = I2CMaster(platform.request("lcd"))
# M2 --------------------------------------------------------------------------------------
self.comb += platform.request("m2_devslp").eq(0) # Enable SATA M2.
# WS2812 ----------------------------------------------------------------------------------
if with_ws2812:
from litex.build.generic_platform import Pins, IOStandard
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.led import WS2812
platform.add_extension([("ws2812", 0, Pins("pmod1:0"),
IOStandard("LVCMOS33"))])
self.submodules.ws2812 = WS2812(platform.request("ws2812"),
nleds=64,
sys_clk_freq=sys_clk_freq)
self.bus.add_slave(name="ws2812",
slave=self.ws2812.bus,
region=SoCRegion(
origin=0x2000_0000,
size=64 * 4,
))
def test_i2c_master_syntax(self):
i2c_master = I2CMaster()
self.assertEqual(hasattr(i2c_master, "pads"), 1)
i2c_master = I2CMaster(Record(I2CMaster.pads_layout))
self.assertEqual(hasattr(i2c_master, "pads"), 1)
