def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Customize Simulation config to match target --------------------------------------------------
from vexriscv_smp import VexRiscvSMP
soc_kwargs["cpu_type"] = "vexriscv_smp"
soc_kwargs["cpu_variant"] = "linux"
soc_kwargs["cpu_cls"] = VexRiscvSMP
args.with_sdram = True
args.sdram_module = "MT41K128M16"
args.sdram_data_width = 16
# Configuration --------------------------------------------------------------------------------
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
for i in range(2):
build = (i == 0)
run = (i == 1)
vns = builder.build(build=build,
run=run,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
if args.gtkwave_savefile:
generate_gtkw_savefile(builder, vns, args.trace_fst)
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC Simulation utility")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
# UART.
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
# ROM.
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
# RAM / SDRAM.
soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
if args.integrated_main_ram_size:
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
elif args.with_sdram:
assert args.ram_init is None
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
# Ethernet.
if args.with_ethernet or args.with_etherbone:
if args.ethernet_phy_model == "sim":
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
elif args.ethernet_phy_model == "xgmii":
sim_config.add_module("xgmii_ethernet",
"xgmii_eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
elif args.ethernet_phy_model == "gmii":
sim_config.add_module("gmii_ethernet",
"gmii_eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
else:
raise ValueError("Unknown Ethernet PHY model: " +
args.ethernet_phy_model)
# I2C.
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
ethernet_phy_model=args.ethernet_phy_model,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
with_spi_flash=args.with_spi_flash,
with_gpio=args.with_gpio,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
spi_flash_init=None if args.spi_flash_init is None else
get_mem_data(args.spi_flash_init, "big"),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
def pre_run_callback(vns):
if args.trace:
generate_gtkw_savefile(builder, vns, args.trace_fst)
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
builder.build(threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end,
interactive=not args.non_interactive,
pre_run_callback=pre_run_callback)
#!/usr/bin/env python3
import os
import os.path
import pprint
import sys
from litex.soc.cores.cpu import CPUS, CPU_VARIANTS
cpus = [c for c in sorted(CPUS.keys()) if c != "None"]
print("Found", len(cpus), "cpus.")
print("They are:")
for c in cpus:
print(" *", c)
# Create a ./requirements/XXX.txt for each CPU.
for c in cpus:
with open('requirements/{}.txt'.format(c), 'w') as f:
f.write("""\
# Install requirements needed to use the {c} soft CPU inside LiteX
-e git+https://github.com/mithro/litex-data-{c}.git#egg=litex-data-{c}
# Install the common requirements that LiteX needs
-r base.txt
""".format(c=c))
# Create a ./requirements/all.txt which includes *all* requirements.
with open('requirements/all.txt', 'w') as f:
f.write("# Install requirements for *all* soft CPUs supported by LiteX!\n")
for c in cpus:
f.write("-r ./requirements/{}.txt\n".format(c))
f.write("""\