def main():
parser = argparse.ArgumentParser(
formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
VexRiscvSMP.args_fill(parser)
args = parser.parse_args()
# build bootrom
subprocess.check_call("make", cwd="bootrom")
# CPU parameters ---------------------------------------------------------------------------
# Do memory accesses through Wishbone and L2 cache when L2 size is configured.
args.with_wishbone_memory = True
VexRiscvSMP.args_read(args)
# SoC creation -----------------------------------------------------------------------------
soc_kwargs = {
"integrated_sram_size": 0x0,
"integrated_rom_size": 0x400,
"l2_size": 0x4000, # Use Wishbone and L2 for memory accesses.
"with_uart": False,
}
rom_data = get_mem_data("bootrom/rom.bin",
endianness="little",
mem_size=soc_kwargs["integrated_rom_size"])
soc_kwargs["integrated_rom_init"] = rom_data
soc = De0SoC(**soc_kwargs)
board_name = "de0nano"
# Build ------------------------------------------------------------------------------------
build_dir = os.path.join("build", board_name)
builder = Builder(soc,
csr_json=os.path.join(build_dir, "csr.json"),
csr_csv=os.path.join(build_dir, "csr.csv"),
compile_software=False)
builder.build(run=args.build)
# DTS --------------------------------------------------------------------------------------
generate_dts(board_name)
compile_dts(board_name)
# Load FPGA bitstream ----------------------------------------------------------------------
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
def main():
parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv Simulation")
parser.add_argument("--with-sdram", action="store_true", help="enable SDRAM support")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC (default=192.168.1.50)")
parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server (default=192.168.1.100)")
parser.add_argument("--trace", action="store_true", help="enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O3", help="compilation optimization level")
VexRiscvSMP.args_fill(parser)
args = parser.parse_args()
VexRiscvSMP.args_read(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
if args.with_ethernet:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})
for i in range(2):
soc = SoCLinux( i!=0,
sdram_module = args.sdram_module,
sdram_data_width = int(args.sdram_data_width),
sdram_verbosity = int(args.sdram_verbosity),
with_ethernet = args.with_ethernet)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i+1), int(args.remote_ip.split(".")[i]))
board_name = "sim"
build_dir = os.path.join("build", board_name)
builder = Builder(soc, output_dir=build_dir,
compile_gateware = i != 0 ,
csr_json = os.path.join(build_dir, "csr.json"))
builder.build(sim_config=sim_config,
run = i != 0,
opt_level = args.opt_level,
trace = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end))
if i == 0:
soc.generate_dts(board_name)
soc.compile_dts(board_name)
def main():
description = "Linux on LiteX-VexRiscv\n\n"
description += "Available boards:\n"
for name in supported_boards.keys():
description += "- " + name + "\n"
parser = argparse.ArgumentParser(
description=description, formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--board", required=True, help="FPGA board")
parser.add_argument("--device", default=None, help="FPGA device")
parser.add_argument("--variant", default=None, help="FPGA board variant")
parser.add_argument("--toolchain",
default=None,
help="Toolchain use to build")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--flash",
action="store_true",
help="Flash bitstream/images (to SPI Flash)")
parser.add_argument("--doc",
action="store_true",
help="Build documentation")
parser.add_argument("--local-ip",
default="192.168.1.50",
help="Local IP address")
parser.add_argument("--remote-ip",
default="192.168.1.100",
help="Remote IP address of TFTP server")
parser.add_argument(
"--spi-data-width",
type=int,
default=8,
help="SPI data width (maximum transfered bits per xfer)")
parser.add_argument("--spi-clk-freq",
type=int,
default=1e6,
help="SPI clock frequency")
VexRiscvSMP.args_fill(parser)
args = parser.parse_args()
# Board(s) selection ---------------------------------------------------------------------------
if args.board == "all":
board_names = list(supported_boards.keys())
else:
args.board = args.board.lower()
args.board = args.board.replace(" ", "_")
board_names = [args.board]
# Board(s) iteration ---------------------------------------------------------------------------
for board_name in board_names:
board = supported_boards[board_name]()
soc_kwargs = Board.soc_kwargs
soc_kwargs.update(board.soc_kwargs)
# CPU parameters ---------------------------------------------------------------------------
# Do memory accesses through Wishbone and L2 cache when L2 size is configured.
args.with_wishbone_memory = soc_kwargs["l2_size"] != 0
VexRiscvSMP.args_read(args)
# SoC parameters ---------------------------------------------------------------------------
if args.device is not None:
soc_kwargs.update(device=args.device)
if args.variant is not None:
soc_kwargs.update(variant=args.variant)
if args.toolchain is not None:
soc_kwargs.update(toolchain=args.toolchain)
if "usb_fifo" in board.soc_capabilities:
soc_kwargs.update(uart_name="usb_fifo")
if "usb_acm" in board.soc_capabilities:
soc_kwargs.update(uart_name="usb_acm")
if "ethernet" in board.soc_capabilities:
soc_kwargs.update(with_ethernet=True)
if "sata" in board.soc_capabilities:
soc_kwargs.update(with_sata=True)
if "framebuffer" in board.soc_capabilities:
soc_kwargs.update(with_video_framebuffer=True)
# SoC creation -----------------------------------------------------------------------------
soc = SoCLinux(board.soc_cls, **soc_kwargs)
board.platform = soc.platform
# SoC peripherals --------------------------------------------------------------------------
if board_name in ["arty", "arty_a7"]:
from litex_boards.platforms.arty import _sdcard_pmod_io
board.platform.add_extension(_sdcard_pmod_io)
if board_name in ["orangecrab"]:
from litex_boards.platforms.orangecrab import feather_i2c
board.platform.add_extension(feather_i2c)
if "mmcm" in board.soc_capabilities:
soc.add_mmcm(2)
if "spiflash" in board.soc_capabilities:
soc.add_spi_flash(dummy_cycles=board.SPIFLASH_DUMMY_CYCLES)
soc.add_constant("SPIFLASH_PAGE_SIZE", board.SPIFLASH_PAGE_SIZE)
soc.add_constant("SPIFLASH_SECTOR_SIZE",
board.SPIFLASH_SECTOR_SIZE)
if "spisdcard" in board.soc_capabilities:
soc.add_spi_sdcard()
if "sdcard" in board.soc_capabilities:
soc.add_sdcard()
if "ethernet" in board.soc_capabilities:
soc.configure_ethernet(local_ip=args.local_ip,
remote_ip=args.remote_ip)
#if "leds" in board.soc_capabilities:
# soc.add_leds()
if "rgb_led" in board.soc_capabilities:
soc.add_rgb_led()
if "switches" in board.soc_capabilities:
soc.add_switches()
if "spi" in board.soc_capabilities:
soc.add_spi(args.spi_data_width, args.spi_clk_freq)
if "i2c" in board.soc_capabilities:
soc.add_i2c()
if "xadc" in board.soc_capabilities:
soc.add_xadc()
if "icap_bitstream" in board.soc_capabilities:
soc.add_icap_bitstream()
soc.configure_boot()
# Build ------------------------------------------------------------------------------------
build_dir = os.path.join("build", board_name)
builder = Builder(soc,
output_dir=os.path.join("build", board_name),
bios_options=["TERM_MINI"],
csr_json=os.path.join(build_dir, "csr.json"),
csr_csv=os.path.join(build_dir, "csr.csv"))
builder.build(run=args.build)
# DTS --------------------------------------------------------------------------------------
soc.generate_dts(board_name)
soc.compile_dts(board_name)
# Load FPGA bitstream ----------------------------------------------------------------------
if args.load:
board.load(
filename=os.path.join(builder.gateware_dir, soc.build_name +
board.bitstream_ext))
# Flash bitstream/images (to SPI Flash) ----------------------------------------------------
if args.flash:
board.flash(
filename=os.path.join(builder.gateware_dir, soc.build_name +
board.bitstream_ext))
# Generate SoC documentation ---------------------------------------------------------------
if args.doc:
soc.generate_doc(board_name)
