def build(self, **kwargs): self.soc.platform.output_dir = self.output_dir os.makedirs(self.gateware_dir, exist_ok=True) os.makedirs(self.software_dir, exist_ok=True) self.soc.finalize() self._generate_includes() self._generate_csr_map() self._generate_mem_region_map() if self.soc.cpu_type is not None: if self.soc.cpu.use_rom: self._prepare_rom_software() self._generate_rom_software(not self.soc.integrated_rom_initialized) if self.soc.integrated_rom_size and self.compile_software: if not self.soc.integrated_rom_initialized: self._initialize_rom_software() if "run" not in kwargs: kwargs["run"] = self.compile_gateware vns = self.soc.build(build_dir=self.gateware_dir, **kwargs) self.soc.do_exit(vns=vns) if self.generate_doc: from litex.soc.doc import generate_docs doc_dir = os.path.join(self.output_dir, "doc") generate_docs(self.soc, doc_dir) os.system(f"sphinx-build -M html {doc_dir} {doc_dir}/_build") return vns
def generate_documentation(self, build_name, **kwargs): from litex.soc.doc import generate_docs generate_docs(self, "documentation".format(build_name), project_name="LitePCIe standalone core", author="Enjoy-Digital") os.system( "sphinx-build -M html documentation/ documentation/_build".format( build_name, build_name))
def run(args, builder, build_kwargs, target_name): # Generate files in the build directory configure_generated_files(builder, args, target_name) # Build & run if not args.sim: # hardware builder.build(**build_kwargs, run=args.build) else: # simulation sim_kwargs = get_sim_kwargs(args) builder.build(**build_kwargs, run=args.build, **sim_kwargs) if args.docs: doc.generate_docs(builder.soc, base_dir="build/documentation", project_name="LiteX Row Hammer Tester", author="Antmicro") if args.load: prog = builder.soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, builder.soc.build_name + ".bit")) if args.load_bios: assert args.rw_bios_mem, 'BIOS memory must be writible' from rowhammer_tester.scripts.utils import RemoteClient, memwrite wb = RemoteClient() wb.open() from litex.soc.integration.common import get_mem_data bios_bin = os.path.join(builder.software_dir, "bios", "bios.bin") rom_data = get_mem_data(bios_bin, "little") print( f"Loading BIOS from: {bios_bin} starting at 0x{wb.mems.rom.base:08x} ..." ) print('Stopping CPU') wb.regs.ctrl_reset.write(0b10) # cpu_rst memwrite(wb, rom_data, base=wb.mems.rom.base) wb.read(wb.mems.rom.base) print('Rebooting CPU') wb.regs.ctrl_reset.write(0) wb.close() if args.flash: prog = builder.soc.platform.create_programmer() prog.flash( 0, os.path.join(builder.gateware_dir, builder.soc.build_name + ".bin"))
def build(self, **kwargs): # Pass Output Directory to Platform. self.soc.platform.output_dir = self.output_dir # Create Gateware/Software directories. _create_dir(self.gateware_dir) _create_dir(self.software_dir) # Finalize the SoC. self.soc.finalize() # Generate Software Includes/Files. self._generate_includes() # Export SoC Mapping. self._generate_csr_map() # Compile the BIOS when the SoC uses it. if self.soc.cpu_type is not None: if self.soc.cpu.use_rom: # Prepare/Generate ROM software. use_bios = ( # BIOS compilation enabled. self.compile_software and # ROM contents has not already been initialized. (not self.soc.integrated_rom_initialized) ) if use_bios: self.soc.check_bios_requirements() self._prepare_rom_software() self._generate_rom_software(compile_bios=use_bios) # Initialize ROM. if use_bios and self.soc.integrated_rom_size: self._initialize_rom_software() # Translate compile_gateware to run. if "run" not in kwargs: kwargs["run"] = self.compile_gateware # Build SoC and pass Verilog Name Space to do_exit. vns = self.soc.build(build_dir=self.gateware_dir, **kwargs) self.soc.do_exit(vns=vns) # Generate SoC Documentation. if self.generate_doc: from litex.soc.doc import generate_docs doc_dir = os.path.join(self.output_dir, "doc") generate_docs(self.soc, doc_dir) os.system(f"sphinx-build -M html {doc_dir} {doc_dir}/_build") return vns
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--flash-offset", default=0x40000, help="Boot offset in SPI Flash") parser.add_argument("--sys-clk-freq", type=float, default=21e6, help="Select system clock frequency") parser.add_argument( "--document-only", action="store_true", help="Do not build a soc. Only generate documentation.") parser.add_argument("--flash", action="store_true", help="Load bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() # Create the SOC soc = BaseSoC(flash_offset=args.flash_offset, sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args)) # Configure command line parameter defaults # Don't build software -- we don't include it since we just jump to SPI flash. builder_kwargs = builder_argdict(args) builder_kwargs["compile_software"] = False if args.document_only: builder_kwargs["compile_gateware"] = False if builder_kwargs["csr_svd"] is None: builder_kwargs["csr_svd"] = "../litex-pac/soc.svd" if builder_kwargs["memory_x"] is None: builder_kwargs["memory_x"] = "../litex-pac/memory.x" # Create and run the builder builder = Builder(soc, **builder_kwargs) builder.build() lxsocdoc.generate_docs(soc, "build/documentation/", project_name="iCEBreaker LiteX RISC-V Example SOC", author="Piotr Esden-Tempski") # If requested load the resulting bitstream onto the iCEBreaker if args.flash: prog = soc.platform.create_programmer() prog.flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--seed", default=0, help="seed to use in nextpnr") parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr") parser.add_argument("--cpu", action="store_true", help="Add a CPU to the build") parser.add_argument( "--debug", action="store_true", help="Add debug features. UART has to be used with the wishbone-tool.") builder_args(parser) soc_core_args(parser) args = parser.parse_args() kwargs = builder_argdict(args) print(kwargs) if args.cpu: kwargs["cpu_type"] = "vexriscv" kwargs["cpu_variant"] = "min" soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed, debug=args.debug, **kwargs) kwargs = builder_argdict(args) # Don't build software -- we don't include it since we just jump # to SPI flash. kwargs["compile_software"] = False builder = Builder(soc, **kwargs) vns = builder.build() soc.do_exit(vns) lxsocdoc.generate_docs(soc, "build/documentation/", project_name="iCEBreaker LiteX Riscv Example SOC", author="Piotr Esden-Tempski")
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--nextpnr-seed", default=0, help="Select nextpnr pseudo random seed") parser.add_argument("--nextpnr-placer", default="heap", choices=["sa", "heap"], help="Select nextpnr placer algorithm") parser.add_argument( "--debug", action="store_true", help= "Enable debug features. (UART has to be used with the wishbone-tool.)") parser.add_argument( "--document-only", action="store_true", help="Do not build a soc. Only generate documentation.") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC(debug=args.debug, **soc_core_argdict(args)) soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed, nextpnr_placer=args.nextpnr_placer) # Don't build software -- we don't include it since we just jump to SPI flash. builder_kwargs = builder_argdict(args) builder_kwargs["compile_software"] = False if args.document_only: builder_kwargs["compile_gateware"] = False builder = Builder(soc, **builder_kwargs) vns = builder.build() soc.do_exit(vns) lxsocdoc.generate_docs(soc, "build/documentation/", project_name="iCEBreaker LiteX Riscv Example SOC", author="Piotr Esden-Tempski")
def run(args, builder, build_kwargs, target_name): # Generate files in the build directory configure_generated_files(builder, args, target_name) # Build & run if not args.sim: # hardware builder.build(**build_kwargs, run=args.build) else: # simulation sim_kwargs = get_sim_kwargs(args) builder.build(**build_kwargs, run=args.build, **sim_kwargs) if args.docs: doc.generate_docs(builder.soc, base_dir="build/documentation", project_name="LiteX Row Hammer Tester", author="Antmicro") if args.load: prog = builder.soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, builder.soc.build_name + ".bit"))
def build(self, **kwargs): # Pass Output Directory to Platform. self.soc.platform.output_dir = self.output_dir # Check if BIOS is used and add software package if so. with_bios = self.soc.cpu_type not in [ None, "zynq7000", "eos-s3", 'gowin_emcu' ] if with_bios: self.add_software_package("bios") # Create Gateware directory. _create_dir(self.gateware_dir) # Create Software directory. # First check if software needs a full re-build and remove software dir if so. if with_bios: software_full_rebuild = False software_variables_mak = os.path.join(self.generated_dir, "variables.mak") if self.compile_software and os.path.exists( software_variables_mak): old_variables_contents = open(software_variables_mak).read() new_variables_contents = self._get_variables_contents() software_full_rebuild = (old_variables_contents != new_variables_contents) _create_dir(self.software_dir, remove_if_exists=software_full_rebuild) # Finalize the SoC. self.soc.finalize() # Generate Software Includes/Files. self._generate_includes(with_bios=with_bios) # Export SoC Mapping. self._generate_csr_map() # Compile the BIOS when the SoC uses it. if self.soc.cpu_type is not None: if self.soc.cpu.use_rom: # Prepare/Generate ROM software. use_bios = ( # BIOS compilation enabled. self.compile_software and # ROM contents has not already been initialized. (not self.soc.integrated_rom_initialized)) if use_bios: self.soc.check_bios_requirements() self._check_meson() self._prepare_rom_software() self._generate_rom_software(compile_bios=use_bios) # Initialize ROM. if use_bios and self.soc.integrated_rom_size: self._initialize_rom_software() # Translate compile_gateware to run. if "run" not in kwargs: kwargs["run"] = self.compile_gateware # Build SoC and pass Verilog Name Space to do_exit. vns = self.soc.build(build_dir=self.gateware_dir, **kwargs) self.soc.do_exit(vns=vns) # Generate SoC Documentation. if self.generate_doc: from litex.soc.doc import generate_docs doc_dir = os.path.join(self.output_dir, "doc") generate_docs(self.soc, doc_dir) os.system(f"sphinx-build -M html {doc_dir} {doc_dir}/_build") return vns
def main(): parser = argparse.ArgumentParser( description="LiteX SoC on Colorlight 5A-75X") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--flash-offset", default=0x100000, help="Boot offset in SPI Flash") parser.add_argument("--sys-clk-freq", type=float, default=50e6, help="Select system clock frequency") parser.add_argument( "--debug", action="store_true", help= "Enable debug features. (UART has to be used with the wishbone-tool.)") parser.add_argument("--board", default="5a-75b", help="Board type: 5a-75b (default) or 5a-75e") parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default), 6.0 or 6.1") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator") parser.add_argument( "--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") parser.add_argument( "--document-only", action="store_true", help="Do not build a soc. Only generate documentation.") parser.add_argument("--flash", action="store_true", help="Load bitstream to flash") parser.add_argument("--load", action="store_true", help="Load bitstream to SRAM") builder_args(parser) soc_core_args(parser) trellis_args(parser) args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) # Create the SOC soc = BaseSoC(board=args.board, revision=args.revision, debug=args.debug, flash_offset=args.flash_offset, sys_clk_freq=int(args.sys_clk_freq), with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, eth_phy=args.eth_phy, use_internal_osc=args.use_internal_osc, sdram_rate=args.sdram_rate, **soc_core_argdict(args)) # Configure command line parameter defaults # Don't build software -- we don't include it since we just jump to SPI flash. builder_kwargs = builder_argdict(args) builder_kwargs["compile_software"] = False if args.document_only: builder_kwargs["compile_gateware"] = False if builder_kwargs["csr_svd"] is None: builder_kwargs["csr_svd"] = "../rust/litex-pac/clSOC.svd" if builder_kwargs["memory_x"] is None: builder_kwargs["memory_x"] = "../rust/litex-pac/memory.x" # Create and run the builder builder = Builder(soc, **builder_kwargs) builder.build(**trellis_argdict(args), run=args.build) lxsocdoc.generate_docs(soc, "build/documentation/", project_name="Colorlight 5A-75x LiteX Riscv SOC", author="DerFetzer") modify_memory_x(builder_kwargs) modify_svd(builder_kwargs) # If requested load the resulting bitstream onto the 5A-75X if args.flash or args.load: prog = ECP5Programmer() if args.load: prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if args.flash: prog.flash( 0x00000000, os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main(): if os.environ['PYTHONHASHSEED'] != "1": print( "PYTHONHASHEED must be set to 1 for consistent validation results. Failing to set this results in non-deterministic compilation results") exit() parser = argparse.ArgumentParser(description="Build the Betrusted Embedded Controller") parser.add_argument( "--revision", choices=["dvt", "pvt"], default="pvt", help="build EC for a particular hardware revision" ) parser.add_argument( "-D", "--document-only", default=False, action="store_true", help="Build docs only" ) parser.add_argument( "--with-dsp", help="use dsp inference in yosys (not all yosys builds have -dsp)", action="store_true" ) parser.add_argument( "--no-cpu", help="disable cpu generation for debugging purposes", action="store_true" ) parser.add_argument( "--placer", choices=["sa", "heap"], help="which placer to use in nextpnr", default="heap", ) parser.add_argument( "--seed", default=0, help="seed to use in nextpnr" ) args = parser.parse_args() output_dir = 'build' compile_gateware = True compile_software = False # this is now done with Rust if args.document_only: compile_gateware = False compile_software = False cpu_type = "vexriscv" cpu_variant = "minimal" cpu_variant = cpu_variant + "+debug" if args.no_cpu: cpu_type = None cpu_variant = None if args.revision == 'dvt' or args.revision == 'pvt': io = io_pvt else: print("Invalid hardware revision") exit(1) platform = BetrustedPlatform(io, revision=args.revision) soc = BaseSoC(platform, cpu_type=cpu_type, cpu_variant=cpu_variant, use_dsp=args.with_dsp, placer=args.placer, pnr_seed=args.seed, output_dir=output_dir) builder = Builder(soc, output_dir=output_dir, csr_csv="build/csr.csv", compile_software=compile_software, compile_gateware=compile_gateware) # If we compile software, pull the code from somewhere other than # the built-in litex "bios" binary, which makes assumptions about # what peripherals are available. if compile_software: builder.software_packages = [ ("bios", os.path.abspath(os.path.join(os.path.dirname(__file__), "bios"))) ] try: vns = builder.build() except OSError: exit(1) soc.do_exit(vns) if not args.document_only: make_multiboot_header(os.path.join(output_dir, "gateware", "multiboot-header.bin"), [ 160, 160, 157696, 262144, 262144 + 32768, ]) with open(os.path.join(output_dir, 'gateware', 'multiboot-header.bin'), 'rb') as multiboot_header_file: multiboot_header = multiboot_header_file.read() with open(os.path.join(output_dir, 'gateware', 'betrusted_ec.bin'), 'rb') as top_file: top = top_file.read() with open(os.path.join(output_dir, 'gateware', 'betrusted_ec_multiboot.bin'), 'wb') as top_multiboot_file: top_multiboot_file.write(multiboot_header) top_multiboot_file.write(top) pad_file(os.path.join(output_dir, 'gateware', 'betrusted_ec.bin'), os.path.join(output_dir, 'gateware', 'betrusted_ec_pad.bin'), 0x1a000) pad_file(os.path.join(output_dir, 'gateware', 'betrusted_ec_multiboot.bin'), os.path.join(output_dir, 'gateware', 'betrusted_ec_multiboot_pad.bin'), 0x1a000) lxsocdoc.generate_docs(soc, "build/documentation", note_pulses=True) lxsocdoc.generate_svd(soc, "build/software")
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--flash-offset", default=0x40000, help="Boot offset in SPI Flash") parser.add_argument("--sys-clk-freq", type=float, default=21e6, help="Select system clock frequency") parser.add_argument("--nextpnr-seed", default=0, help="Select nextpnr pseudo random seed") parser.add_argument("--nextpnr-placer", default="heap", choices=["sa", "heap"], help="Select nextpnr placer algorithm") parser.add_argument( "--debug", action="store_true", help= "Enable debug features. (UART has to be used with the wishbone-tool.)") parser.add_argument( "--document-only", action="store_true", help="Do not build a soc. Only generate documentation.") parser.add_argument("--flash", action="store_true", help="Load bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() # Create the SOC soc = BaseSoC(debug=args.debug, flash_offset=args.flash_offset, sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args)) soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed, nextpnr_placer=args.nextpnr_placer) # Configure command line parameter defaults # Don't build software -- we don't include it since we just jump to SPI flash. builder_kwargs = builder_argdict(args) builder_kwargs["compile_software"] = False if args.document_only: builder_kwargs["compile_gateware"] = False if builder_kwargs["csr_svd"] is None: builder_kwargs["csr_svd"] = "../rust/icebesoc-pac/iCEBESOC.svd" if builder_kwargs["memory_x"] is None: builder_kwargs["memory_x"] = "../rust/icebesoc-pac/memory.x" # Create and run the builder builder = Builder(soc, **builder_kwargs) builder.build() lxsocdoc.generate_docs(soc, "build/documentation/", project_name="iCEBreaker LiteX Riscv Example SOC", author="Piotr Esden-Tempski") # If requested load the resulting bitstream onto the iCEBreaker if args.flash: IceStormProgrammer().flash(0x00000000, "soc_basesoc_icebreaker/gateware/top.bin")
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab") parser.add_argument( "--gateware-toolchain", dest="toolchain", default="trellis", help="gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) parser.add_argument("--sys-clk-freq", default=48e6, help="system clock frequency (default=48MHz)") parser.add_argument("--revision", default="0.2", help="Board Revision {0.1, 0.2} (default=0.2)") parser.add_argument("--device", default="25F", help="ECP5 device (default=25F)") parser.add_argument("--sdram-device", default="MT41K64M16", help="ECP5 device (default=MT41K64M16)") parser.add_argument("--docs-only", default=False, action='store_true', help="Create docs") args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **argdict(args)) if args.docs_only: args.no_compile_software = True args.no_compile_gateware = True builder = Builder(soc, **builder_argdict(args)) soc.write_usb_csr(builder.generated_dir) # Build gateware builder_kargs = trellis_argdict( args) if args.toolchain == "trellis" else {} vns = builder.build(**builder_kargs) soc.do_exit(vns) generate_docs(soc, "build/documentation/", project_name="OrangeCrab Test SoC", author="Greg Davill") input_config = os.path.join(builder.output_dir, "gateware", f"{soc.platform.name}.config") # create compressed bitstream (ECP5 specific), (Note that `-spimode qspi` sometimes doesn't load over JTAG) output_bitstream = os.path.join(builder.gateware_dir, f"{soc.platform.name}.bit") os.system( f"ecppack --freq 38.8 --spimode qspi --compress --input {input_config} --bit {output_bitstream}" ) dfu_file = os.path.join(builder.gateware_dir, f"{soc.platform.name}.dfu") shutil.copyfile(output_bitstream, dfu_file) os.system(f"dfu-suffix -v 1209 -p 5af0 -a {dfu_file}")
def generate_doc(self, board_name): from litex.soc.doc import generate_docs doc_dir = os.path.join("build", board_name, "doc") generate_docs(self, doc_dir) os.system("sphinx-build -M html {}/ {}/_build".format(doc_dir, doc_dir))
def main(): parser = argparse.ArgumentParser(description="Build Fomu Main Gateware") parser.add_argument( "--boot-source", choices=["spi", "rand", "bios"], default="bios", help="where to have the CPU obtain its executable code from") parser.add_argument( "--document-only", default=False, action="store_true", help="Don't build gateware or software, only build documentation") parser.add_argument("--revision", choices=["evt", "dvt", "pvt", "hacker"], required=True, help="build foboot for a particular hardware revision") parser.add_argument( "--bios", help="use specified file as a BIOS, rather than building one") parser.add_argument("--with-debug", help="enable debug support", choices=["usb", "uart", "spi", None]) parser.add_argument( "--with-dsp", help="use dsp inference in yosys (not all yosys builds have -dsp)", action="store_true") parser.add_argument("--no-cpu", help="disable cpu generation for debugging purposes", action="store_true") parser.add_argument("--placer", choices=["sa", "heap"], default="heap", help="which placer to use in nextpnr") parser.add_argument("--seed", default=0, help="seed to use in nextpnr") parser.add_argument( "--export-random-rom-file", help="Generate a random ROM file and save it to a file") args = parser.parse_args() output_dir = 'build' if args.export_random_rom_file is not None: size = 0x2000 def xorshift32(x): x = x ^ (x << 13) & 0xffffffff x = x ^ (x >> 17) & 0xffffffff x = x ^ (x << 5) & 0xffffffff return x & 0xffffffff def get_rand(x): out = 0 for i in range(32): x = xorshift32(x) if (x & 1) == 1: out = out | (1 << i) return out & 0xffffffff seed = 1 with open(args.export_random_rom_file, "w", newline="\n") as output: for d in range(int(size / 4)): seed = get_rand(seed) print("{:08x}".format(seed), file=output) return 0 compile_software = False if (args.boot_source == "bios" or args.boot_source == "spi") and args.bios is None: compile_software = True cpu_type = "vexriscv" cpu_variant = "minimal" if args.with_debug: cpu_variant = cpu_variant + "+debug" if args.no_cpu: cpu_type = None cpu_variant = None compile_gateware = True if args.document_only: compile_gateware = False compile_software = False warmboot_offsets = [ 160, 160, 157696, 262144, 262144 + 32768, ] os.environ["LITEX"] = "1" # Give our Makefile something to look for platform = Platform(revision=args.revision) soc = BaseSoC(platform, cpu_type=cpu_type, cpu_variant=cpu_variant, debug=args.with_debug, boot_source=args.boot_source, bios_file=args.bios, use_dsp=args.with_dsp, placer=args.placer, pnr_seed=int(args.seed), output_dir=output_dir, warmboot_offsets=warmboot_offsets[1:]) builder = Builder(soc, output_dir=output_dir, csr_csv="build/csr.csv", csr_svd="build/soc.svd", compile_software=compile_software, compile_gateware=compile_gateware) if compile_software: builder.software_packages = [ ("bios", os.path.abspath( os.path.join(os.path.dirname(__file__), "..", "sw"))) ] vns = builder.build() soc.do_exit(vns) lxsocdoc.generate_docs(soc, "build/documentation/", project_name="Fomu Bootloader", author="Sean Cross") if not args.document_only: make_multiboot_header( os.path.join(output_dir, "gateware", "multiboot-header.bin"), warmboot_offsets) with open(os.path.join(output_dir, 'gateware', 'multiboot-header.bin'), 'rb') as multiboot_header_file: multiboot_header = multiboot_header_file.read() with open(os.path.join(output_dir, 'gateware', 'top.bin'), 'rb') as top_file: top = top_file.read() with open( os.path.join(output_dir, 'gateware', 'top-multiboot.bin'), 'wb') as top_multiboot_file: top_multiboot_file.write(multiboot_header) top_multiboot_file.write(top) print("""Foboot build complete. Output files: {}/gateware/top.bin Bitstream file. Load this onto the FPGA for testing. {}/gateware/top-multiboot.bin Multiboot-enabled bitstream file. Flash this onto FPGA ROM. {}/gateware/top.v Source Verilog file. Useful for debugging issues. {}/software/include/generated/ Directory with header files for API access. {}/software/bios/bios.elf ELF file for debugging bios. """.format(output_dir, output_dir, output_dir, output_dir, output_dir))
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--docs", action="store_true", help="Generate documentation") parser.add_argument( "--toolchain", default="vivado", help="Gateware toolchain to use, vivado (default) or symbiflow") parser.add_argument("--sim", action="store_true", help="Build and run in simulation mode") parser.add_argument("--sys-clk-freq", default="100e6", help="TODO") parser.add_argument("--no-memory-bist", action="store_true", help="Enable memory BIST module") parser.add_argument("--ip-address", default="192.168.100.50", help="Use given IP address") parser.add_argument("--mac-address", default="0x10e2d5000001", help="Use given MAC address") parser.add_argument("--udp-port", default="1234", help="Use given UDP port") builder_args(parser) soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() # Force defaults to no CPU soc_kwargs = soc_core_argdict(args) soc_kwargs.update( dict( cpu_type=None, no_timer=True, no_ctrl=True, no_uart=True, uart_name="stub", integrated_rom_size=0, integrated_sram_size=0, integrated_main_ram_size=0, )) sys_clk_freq = int(float(args.sys_clk_freq)) soc = BaseSoC(toolchain=args.toolchain, args=args, sys_clk_freq=sys_clk_freq, ip_address=args.ip_address, mac_address=int(args.mac_address, 0), udp_port=int(args.udp_port, 0), **soc_kwargs) # FIXME: try to generate to build/ and make the scripts use that version? script_dir = os.path.dirname(os.path.abspath(os.path.realpath(__file__))) soc.generate_sdram_phy_py_header( os.path.join(script_dir, "..", "scripts", "sdram_init.py")) builder_kwargs = builder_argdict(args) builder_kwargs["csr_csv"] = os.path.join(script_dir, "..", "scripts", "csr.csv") builder = Builder(soc, **builder_kwargs) build_kwargs = vivado_build_argdict(args) if not args.sim: builder.build(**build_kwargs, run=args.build) else: sim_config = SimConfig() sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq) sim_config.add_module("ethernet", "eth", args={ "interface": "arty", "ip": args.ip_address }) del build_kwargs['synth_mode'] builder.build(**build_kwargs, run=args.build, sim_config=sim_config, trace=True, trace_fst=False) if args.docs: doc.generate_docs(soc, base_dir="build/documentation", project_name="LiteX Row Hammer Tester", author="Antmicro") if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--docs", action="store_true", help="Generate documentation") parser.add_argument( "--toolchain", default="vivado", help="Gateware toolchain to use, vivado (default) or symbiflow") parser.add_argument("--sim", action="store_true", help="Build and run in simulation mode") parser.add_argument("--sys-clk-freq", default="100e6", help="TODO") parser.add_argument("--no-memory-bist", action="store_true", help="Enable memory BIST module") parser.add_argument("--ip-address", default="192.168.100.50", help="Use given IP address") parser.add_argument("--mac-address", default="0x10e2d5000001", help="Use given MAC address") parser.add_argument("--udp-port", default="1234", help="Use given UDP port") parser.add_argument("--no-payload-executor", action="store_true", help="Disable Payload Executor module") builder_args(parser) soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() # Force defaults to no CPU soc_kwargs = soc_core_argdict(args) soc_kwargs.update( dict( cpu_type=None, no_timer=True, no_ctrl=True, no_uart=True, uart_name="stub", integrated_rom_size=0, integrated_sram_size=0, integrated_main_ram_size=0, )) sys_clk_freq = int(float(args.sys_clk_freq)) soc = BaseSoC(toolchain=args.toolchain, args=args, sys_clk_freq=sys_clk_freq, ip_address=args.ip_address, mac_address=int(args.mac_address, 0), udp_port=int(args.udp_port, 0), **soc_kwargs) builder_kwargs = builder_argdict(args) if args.sim: # always build in the build/arty/ directory builder_kwargs["output_dir"] = os.path.join('build', 'arty') builder = Builder(soc, **builder_kwargs) build_kwargs = vivado_build_argdict(args) # Generate files in the build directory builder.csr_csv = os.path.join(builder.output_dir, 'csr.csv') soc.generate_sdram_phy_py_header( os.path.join(builder.output_dir, "sdram_init.py")) with open(os.path.join(builder.output_dir, 'defs.csv'), 'w', newline='') as f: writer = csv.writer(f) writer.writerows([ ('IP_ADDRESS', args.ip_address), ('MAC_ADDRESS', args.mac_address), ('UDP_PORT', args.udp_port), ]) if not args.sim: builder.build(**build_kwargs, run=args.build) else: sim_config = SimConfig() sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq) sim_config.add_module("ethernet", "eth", args={ "interface": "arty", "ip": args.ip_address }) del build_kwargs['synth_mode'] builder.build(**build_kwargs, run=args.build, sim_config=sim_config, trace=True, trace_fst=False) if args.docs: doc.generate_docs(soc, base_dir="build/documentation", project_name="LiteX Row Hammer Tester", author="Antmicro") if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))