def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_spi_flash=args.with_spi_flash,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
from litex.build.openfpgaloader import OpenFPGALoader
prog = OpenFPGALoader("trion_t120_bga576")
prog.flash(0, builder.get_bitstream_filename(mode="flash",
ext=".hex")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE10-Nano")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
target_group.add_argument("--with-mister-sdram",
action="store_true",
help="Enable SDRAM with MiSTer expansion board.")
target_group.add_argument(
"--with-mister-video-terminal",
action="store_true",
help="Enable Video Terminal with Mister expansion board.")
target_group.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_mister_sdram=args.with_mister_sdram,
with_mister_video_terminal=args.with_mister_video_terminal,
sdram_rate=args.sdram_rate,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX Test SoC on OS-FPGA")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build design.")
target_group.add_argument("--toolchain",
default="raptor",
help="FPGA toolchain.")
target_group.add_argument("--device",
default="gemini",
help="FPGA device.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
platform = Platform(toolchain=args.toolchain, device=args.device)
soc = BaseSoC(platform, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
if args.build:
builder.build()
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Beaglewire")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--bios-flash-offset",
default="0x60000",
help="BIOS offset in SPI Flash.")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(bios_flash_offset=int(args.bios_flash_offset, 0),
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on MiniSpartan6")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=80e6,
help="System clock frequency.")
target_group.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
sdram_rate=args.sdram_rate,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on ADI ADRV2CRR-FMC")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=150e6,
help="System clock frequency (default: 150 MHz)")
target_group.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support")
target_group.add_argument("--driver",
action="store_true",
help="Generate PCIe driver")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_pcie=args.with_pcie,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on RZ-EasyFPGA")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_rate = args.sdram_rate,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_spi_flash = args.with_spi_flash,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_phy = args.eth_phy,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
from litex.build.openfpgaloader import OpenFPGALoader
prog = OpenFPGALoader("trion_t120_bga576")
prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".hex")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--board", default="5a-75b", help="Board type (5a-75b or 5a-75e).")
target_group.add_argument("--revision", default="7.0", type=str, help="Board revision (6.0, 6.1, 7.0 or 8.0).")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
target_group.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board, revision=args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_phy = args.eth_phy,
use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC Blackmagic Decklink Mini 4K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=148.5e6, help="System clock frequency.")
pcieopts = target_group.add_mutually_exclusive_group()
pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
with_sata = args.with_sata,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on ECP5 Evaluation Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq",
default=60e6,
help="System clock frequency.")
target_group.add_argument(
"--x5-clk-freq",
type=int,
help="Use X5 oscillator as system clock at the specified frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
x5_clk_freq=args.x5_clk_freq,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on iCEBreaker")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",
default=24e6,
help="System clock frequency.")
target_group.add_argument("--bios-flash-offset",
default="0x40000",
help="BIOS offset in SPI Flash.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(bios_flash_offset=int(args.bios_flash_offset, 0),
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".bin")) # FIXME
if args.flash:
flash(int(args.bios_flash_offset, 0))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="Generic LiteX SoC")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("platform", help="Module name of the platform to build for.")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default=None, help="FPGA toolchain.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
platform_module = importlib.import_module(args.platform)
platform_kwargs = {}
if args.toolchain is not None:
platform_kwargs["toolchain"] = args.toolchain
platform = platform_module.Platform(**platform_kwargs)
soc = BaseSoC(platform,**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Versa ECP5")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--device", default="LFE5UM5G", help="FPGA device (LFE5UM5G or LFE5UM).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
device = args.device,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_phy = args.eth_phy,
toolchain = args.toolchain,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Trenz TE0725")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="flash"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Fomu")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
dfu_flash_offset = 0x40000
soc = BaseSoC(
bios_flash_offset = dfu_flash_offset + int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.flash:
flash(builder.output_dir, soc.build_name, int(args.bios_flash_offset, 0))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Acorn CLE-101/215(+)")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream.")
target_group.add_argument(
"--variant",
default="cle-215+",
help="Board variant (cle-215+, cle-215 or cle-101).")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
pcieopts = target_group.add_mutually_exclusive_group()
pcieopts.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support.")
target_group.add_argument("--driver",
action="store_true",
help="Generate PCIe driver.")
target_group.add_argument(
"--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support (requires SDCard adapter on P2).")
pcieopts.add_argument("--with-sata",
action="store_true",
help="Enable SATA support (over PCIe2SATA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(variant=args.variant,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_pcie=args.with_pcie,
with_sata=args.with_sata,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency.")
target_group.add_argument("--revision",
default="1.0",
help="Board Revision (1.0).")
target_group.add_argument("--device",
default="85F",
help="ECP5 device (25F, 45F, 85F).")
target_group.add_argument(
"--sdram-device",
default="MT41K64M16",
help=
"SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Add Ethernet.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Add EtherBone.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
help="Ethernet/Etherbone IP address.")
target_group.add_argument(
"--eth-dynamic-ip",
action="store_true",
help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
target_group.add_argument(
"--with-syzygy-gpio",
action="store_true",
help="Enable GPIOs through SYZYGY Breakout on Port-A.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(toolchain=args.toolchain,
revision=args.revision,
device=args.device,
sdram_device=args.sdram_device,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_dynamic_ip=args.eth_dynamic_ip,
with_spi_flash=args.with_spi_flash,
with_syzygy_gpio=args.with_syzygy_gpio,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on QMTECH Wukong Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument("--board-version",
default=1,
help="Board version (1 or 2).")
target_group.add_argument("--speed-grade",
default=-1,
help="FPGA speed grade (-1 or -2).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
speed_grade = int(args.speed_grade)
if speed_grade not in [-1, -2]:
raise ValueError("Speed grade {} unsupported".format(speed_grade))
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
board_version=int(args.board_version),
speed_grade=speed_grade,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
soc.add_spi_sdcard()
if args.with_sdcard:
if int(args.board_version) < 2:
soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight I5")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--board", default="i5", help="Board type (i5).")
target_group.add_argument("--revision",
default="7.0",
type=str,
help="Board revision (7.0).")
target_group.add_argument("--sys-clk-freq",
default=60e6,
help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
target_group.add_argument("--remote-ip",
default="192.168.1.100",
help="Remote IP address of TFTP server.")
target_group.add_argument("--local-ip",
default="192.168.1.50",
help="Local IP address.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
target_group.add_argument("--eth-phy",
default=0,
type=int,
help="Ethernet PHY (0 or 1).")
target_group.add_argument("--use-internal-osc",
action="store_true",
help="Use internal oscillator.")
target_group.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board,
revision=args.revision,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
local_ip=args.local_ip,
remote_ip=args.remote_ip,
eth_phy=args.eth_phy,
use_internal_osc=args.use_internal_osc,
sdram_rate=args.sdram_rate,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
soc.platform.add_extension(colorlight_i5._sdcard_pmod_io)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH EP4CE15")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--variant",
default="ep4ce15",
help="Board variant (ep4ce15 or ep4ce55).")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
target_group.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group.add_argument(
"--with-daughterboard",
action="store_true",
help="Board plugged into the QMTech daughterboard.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address.")
target_group.add_argument(
"--eth-dynamic-ip",
action="store_true",
help="Enable dynamic Ethernet IP addresses setting.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(variant=args.variant,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_daughterboard=args.with_daughterboard,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_dynamic_ip=args.eth_dynamic_ip,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
sdram_rate=args.sdram_rate,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on STLV7325")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address.")
target_group.add_argument(
"--eth-dynamic-ip",
action="store_true",
help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support.")
target_group.add_argument("--driver",
action="store_true",
help="Generate PCIe driver.")
target_group.add_argument("--with-sata",
action="store_true",
help="Enable SATA support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_dynamic_ip=args.eth_dynamic_ip,
with_pcie=args.with_pcie,
with_sata=args.with_sata,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Arty A7")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument(
"--toolchain",
default="vivado",
help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream.")
target_group.add_argument("--variant",
default="a7-35",
help="Board variant (a7-35 or a7-100).")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address.")
target_group.add_argument(
"--eth-dynamic-ip",
action="store_true",
help="Enable dynamic Ethernet IP addresses setting.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
target_group.add_argument("--sdcard-adapter",
type=str,
help="SDCard PMOD adapter (digilent or numato).")
target_group.add_argument("--with-jtagbone",
action="store_true",
help="Enable JTAGbone support.")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
target_group.add_argument(
"--with-pmod-gpio",
action="store_true",
help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(variant=args.variant,
toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_dynamic_ip=args.eth_dynamic_ip,
with_jtagbone=args.with_jtagbone,
with_spi_flash=args.with_spi_flash,
with_pmod_gpio=args.with_pmod_gpio,
**soc_core_argdict(args))
if args.sdcard_adapter == "numato":
soc.platform.add_extension(arty._numato_sdcard_pmod_io)
else:
soc.platform.add_extension(arty._sdcard_pmod_io)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(
args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on LiteX Acorn Baseboard")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream to SPI Flash.")
target_group.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
target_group.add_argument("--with-lcd",
action="store_true",
help="Enable OLED LCD support.")
target_group.add_argument("--with-ws2812",
action="store_true",
help="Enable WS2812 on PMOD1:0.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_spi_flash=args.with_spi_flash,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_video_terminal=args.with_video_terminal,
with_lcd=args.with_lcd,
with_ws2812=args.with_ws2812,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(
None,
prog.load_bitstream(builder.get_bitstream_filename(mode="flash")))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on LPDDR4 Test Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument("--iodelay-clk-freq",
default=200e6,
help="IODELAYCTRL frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Add Ethernet.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Add EtherBone.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
help="Ethernet/Etherbone IP address.")
target_group.add_argument(
"--eth-dynamic-ip",
action="store_true",
help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--eth-reset-time",
default="10e-3",
help="Duration of Ethernet PHY reset")
target_group.add_argument("--with-hyperram",
action="store_true",
help="Add HyperRAM.")
target_group.add_argument("--with-sdcard",
action="store_true",
help="Add SDCard.")
target_group.add_argument("--with-jtagbone",
action="store_true",
help="Add JTAGBone.")
target_group.add_argument("--with-uartbone",
action="store_true",
help="Add UartBone on 2nd serial.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
iodelay_clk_freq=int(float(args.iodelay_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_dynamic_ip=args.eth_dynamic_ip,
eth_reset_time=args.eth_reset_time,
with_hyperram=args.with_hyperram,
with_sdcard=args.with_sdcard,
with_jtagbone=args.with_jtagbone,
with_uartbone=args.with_uartbone,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build(**vivado_build_argdict(args), run=args.build)
builder.soc.generate_sdram_phy_py_header(
os.path.join(builder.output_dir, "sdram_init.py"))
# LiteDRAM settings (controller, phy, geom, timing)
with open(os.path.join(builder.output_dir, 'litedram_settings.json'),
'w') as f:
json.dump(builder.soc.sdram.controller.settings,
f,
cls=LiteDRAMSettingsEncoder,
indent=4)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTech XC7A35T")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain",
default="vivado",
help="FPGA toolchain (vivado or symbiflow).")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument(
"--with-daughterboard",
action="store_true",
help="Board plugged into the QMTech daughterboard.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
type=str,
help="Ethernet/Etherbone IP address.")
target_group.add_argument(
"--eth-dynamic-ip",
action="store_true",
help="Enable dynamic Ethernet IP addresses setting.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
target_group.add_argument("--with-jtagbone",
action="store_true",
help="Enable Jtagbone support.")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (VGA).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_daughterboard=args.with_daughterboard,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_dynamic_ip=args.eth_dynamic_ip,
with_jtagbone=args.with_jtagbone,
with_spi_flash=args.with_spi_flash,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(
args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on LPDDR4 Test Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
target_group.add_argument("--iodelay-clk-freq",
default=200e6,
help="IODELAYCTRL frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Add Ethernet.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Add EtherBone.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
help="Ethernet/Etherbone IP address.")
target_group.add_argument(
"--eth-dynamic-ip",
action="store_true",
help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-hyperram",
action="store_true",
help="Add HyperRAM.")
target_group.add_argument("--with-sdcard",
action="store_true",
help="Add SDCard.")
target_group.add_argument("--with-jtagbone",
action="store_true",
help="Add JTAGBone.")
target_group.add_argument("--with-uartbone",
action="store_true",
help="Add UartBone on 2nd serial.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
iodelay_clk_freq=int(float(args.iodelay_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
eth_dynamic_ip=args.eth_dynamic_ip,
with_hyperram=args.with_hyperram,
with_sdcard=args.with_sdcard,
with_jtagbone=args.with_jtagbone,
with_uartbone=args.with_uartbone,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Trellis Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency.")
target_group.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI).")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
target_group.add_argument(
"--with-pmod-gpio",
action="store_true",
help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
with_pmod_gpio=args.with_pmod_gpio,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ULX3S")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
target_group.add_argument(
"--device",
default="LFE5U-45F",
help="FPGA device (LFE5U-12F, LFE5U-25F, LFE5U-45F or LFE5U-85F).")
target_group.add_argument("--revision",
default="2.0",
help="Board revision (2.0 or 1.7).")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
target_group.add_argument(
"--sdram-module",
default="MT48LC16M16",
help="SDRAM module (MT48LC16M16, AS4C32M16 or AS4C16M16).")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
target_group.add_argument("--with-oled",
action="store_true",
help="Enable SDD1331 OLED support.")
target_group.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(device=args.device,
revision=args.revision,
toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
sdram_module_cls=args.sdram_module,
sdram_rate=args.sdram_rate,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
with_spi_flash=args.with_spi_flash,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
if args.with_oled:
soc.add_oled()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
