def __init__(self, platform, spiboot=False, **kwargs): Sim.__init__(self, platform, custom_clocks=local_clocks, spiboot=spiboot, **kwargs) # SoC magic is in here # add a key for the i2s_duplex sim block SoCCore.mem_map["i2s_duplex"] = 0xe0001000 # shallow fifodepth allows us to work the end points a bit faster in simulation self.submodules.i2s_duplex = S7I2S(platform.request("i2s", 0), fifo_depth=8) self.bus.add_slave( "i2s_duplex", self.i2s_duplex.bus, SoCRegion(origin=self.mem_map["i2s_duplex"], size=0x4, cached=False)) self.add_csr("i2s_duplex") self.add_interrupt("i2s_duplex") self.submodules.audio = S7I2S(platform.request("i2s", 1), fifo_depth=8) self.bus.add_slave( "audio", self.audio.bus, SoCRegion(origin=self.mem_map["audio"], size=0x4, cached=False)) self.add_csr("audio") self.add_interrupt("audio")
def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", with_led_chaser=True, **kwargs): platform = crosslink_nx_vip.Platform(toolchain=toolchain) platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") # Disable Integrated SRAM since we want to instantiate LRAM specifically for it kwargs["integrated_sram_size"] = 0 # SoCCore -----------------------------------------_---------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Crosslink-NX VIP Input Board", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) if hyperram == "none": # 128KB LRAM (used as SRAM) ------------------------------------------------------------ size = 128*kB self.submodules.spram = NXLRAM(32, size) self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(size=size)) else: # Use HyperRAM generic PHY as SRAM ----------------------------------------------------- size = 8*1024*kB hr_pads = platform.request("hyperram", int(hyperram)) self.submodules.hyperram = HyperRAM(hr_pads) self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = Cat(*[platform.request("user_led", i) for i in range(4)]), sys_clk_freq = sys_clk_freq)
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs): platform = lattice_ice40up5k_evn.Platform() # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs[ "cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__( self, platform, sys_clk_freq, ident="LiteX SoC on Lattice iCE40UP5k EVN breakout board", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=128 * kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * kB)) # SPI Flash -------------------------------------------------------------------------------- # 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA from litespi.modules import N25Q032A from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=N25Q032A(Codes.READ_1_1_1)) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset, size=32 * kB, linker=True)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led_n"), sys_clk_freq=sys_clk_freq) # Add a UART-Wishbone bridge ----------------------------------------- debug_uart = False if debug_uart: # This will add a bridge on the second serial port defined in platform from litex.soc.cores.uart import UARTWishboneBridge self.submodules.uart_bridge = UARTWishboneBridge( platform.request("serial"), sys_clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone)
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True, with_video_terminal=False, **kwargs): platform = icebreaker.Platform() platform.add_extension(icebreaker.break_off_pmod) # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs[ "cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on iCEBreaker", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=64 * kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * kB)) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="1x", dummy_cycles=8) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset, size=32 * kB, linker=True)) # Video ------------------------------------------------------------------------------------ if with_video_terminal: platform.add_extension(icebreaker.dvi_pmod) self.submodules.videophy = VideoDVIPHY(platform.request("dvi"), clock_domain="sys") self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="sys") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), revision="v1", **kwargs): platform = icebreaker_bitsy.Platform(revision=revision) # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs[ "cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on iCEBreaker-bitsy", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) ----------------------------------------------- self.submodules.spram = Up5kSPRAM(size=128 * kB) self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * kB)) self.bus.add_region( "sram", SoCRegion(origin=self.bus.regions["psram"].origin + 0 * kB, size=64 * kB, linker=True)) if not self.integrated_main_ram_size: self.bus.add_region( "main_ram", SoCRegion(origin=self.bus.regions["psram"].origin + 64 * kB, size=64 * kB, linker=True)) # SPI Flash -------------------------------------------------------------------------------- from litespi.modules import W25Q128JV from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset, size=32 * kB, linker=True))
def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs): platform = alinx_axu2cga.Platform() if kwargs.get("cpu_type", None) == "zynqmp": kwargs['integrated_sram_size'] = 0 kwargs['with_uart'] = False self.mem_map = { 'csr': 0x8000_0000, # Zynq GP0 default } # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXU2CGA", **kwargs) # ZynqMP Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynqmp": self.cpu.config.update(platform.psu_config) # Connect AXI HPM0 LPD to the SoC wb_lpd = wishbone.Interface() self.submodules += axi.AXI2Wishbone( axi=self.cpu.add_axi_gp_master(2, 32), wishbone=wb_lpd, base_address=self.mem_map['csr']) self.add_wb_master(wb_lpd) self.bus.add_region( "sram", SoCRegion(origin=self.cpu.mem_map["sram"], size=1 * 1024 * 1024 * 1024) # DDR ) self.bus.add_region( "rom", SoCRegion(origin=self.cpu.mem_map["rom"], size=512 * 1024 * 1024 // 8, linker=True)) self.constants['CONFIG_CLOCK_FREQUENCY'] = 1199880127 use_psu_clk = True else: use_psu_clk = False # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, use_psu_clk) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs): kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM platform = fomu_pvt.Platform() # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs[ "cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # Serial ----------------------------------------------------------------------------------- # FIXME: do proper install of ValentyUSB. os.system( "git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri" ) sys.path.append("valentyusb") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Fomu", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=128 * kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * kB)) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="1x", dummy_cycles=8) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset, size=32 * kB, linker=True)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led_n"), sys_clk_freq=sys_clk_freq)
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True, with_video_terminal=False, **kwargs): platform = muselab_icesugar.Platform() # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant if kwargs.get("cpu_type", "vexriscv") == "vexriscv": kwargs["cpu_variant"] = "lite" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Muselab iCESugar", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=64 * kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * kB)) # SPI Flash -------------------------------------------------------------------------------- from litespi.modules import W25Q64FV from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=W25Q64FV(Codes.READ_1_1_1), with_master=False) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.bus.regions["spiflash"].origin + bios_flash_offset, size=32 * kB, linker=True)) self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: led_pads = platform.request_all("user_led_n") self.submodules.leds = LedChaser(pads=led_pads, sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq, with_led_chaser=True, **kwargs): platform = digilent_zedboard.Platform() if kwargs.get("cpu_type", None) == "zynq7000": kwargs['integrated_sram_size'] = 0 # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zedboard", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": self.cpu.set_ps7( name="Zynq", preset="ZedBoard", config={'PCW_FPGA0_PERIPHERAL_FREQMHZ': sys_clk_freq / 1e6}) # Connect AXI GP0 to the SoC wb_gp0 = wishbone.Interface() self.submodules += axi.AXI2Wishbone( axi=self.cpu.add_axi_gp_master(), wishbone=wb_gp0, base_address=self.mem_map["csr"]) self.add_wb_master(wb_gp0) self.bus.add_region( "sram", SoCRegion(origin=self.cpu.mem_map["sram"], size=512 * 1024 * 1024 - self.cpu.mem_map["sram"])) self.bus.add_region( "rom", SoCRegion(origin=self.cpu.mem_map["rom"], size=256 * 1024 * 1024 // 8, linker=True)) self.constants['CONFIG_CLOCK_FREQUENCY'] = 666666687 use_ps7_clk = True else: use_ps7_clk = False # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs): platform = lattice_ice40up5k_evn.Platform() # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__( self, platform, sys_clk_freq, ident="LiteX SoC on Lattice iCE40UP5k EVN breakout board", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=128 * kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * kB)) # SPI Flash -------------------------------------------------------------------------------- # 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA from litespi.modules import N25Q032A from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=N25Q032A(Codes.READ_1_1_1)) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.bus.regions["spiflash"].origin + bios_flash_offset, size=32 * kB, linker=True)) self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led_n"), sys_clk_freq=sys_clk_freq) # Add a UARTBone bridge -------------------------------------------------------------------- debug_uart = False if debug_uart: self.add_uartbone(name="serial")
def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), **kwargs): platform = tinyfpga_bx.Platform() # Disable Integrated ROM since too large for iCE40. kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on TinyFPGA BX", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("clk16")) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="1x", dummy_cycles=8) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( origin = self.mem_map["spiflash"] + bios_flash_offset, size = 32*kB, linker = True) ) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1", with_led_chaser=True, **kwargs): platform = tec0117.Platform() # Disable Integrated ROM. kwargs["integrated_rom_size"] = 0 # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on TEC0117", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- from litespi.modules import W74M64FV from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=W74M64FV(Codes.READ_1_1_4), with_master=False) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( origin = self.bus.regions["spiflash"].origin + bios_flash_offset, size = 32*kB, linker = True) ) self.cpu.set_reset_address(self.bus.regions["rom"].origin) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: class SDRAMPads: def __init__(self): self.clk = platform.request("O_sdram_clk") self.cke = platform.request("O_sdram_cke") self.cs_n = platform.request("O_sdram_cs_n") self.cas_n = platform.request("O_sdram_cas_n") self.ras_n = platform.request("O_sdram_ras_n") self.we_n = platform.request("O_sdram_wen_n") self.dm = platform.request("O_sdram_dqm") self.a = platform.request("O_sdram_addr") self.ba = platform.request("O_sdram_ba") self.dq = platform.request("IO_sdram_dq") sdram_pads = SDRAMPads() sdram_clk = ClockSignal("sys2x" if sdram_rate == "1:2" else "sys") # FIXME: use phase shift from PLL. self.specials += DDROutput(0, 1, sdram_pads.clk, sdram_clk) sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. l2_cache_size = 128, ) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(200e6), with_spi_flash=False, with_hyperram=False, **kwargs): platform = efinix_titanium_ti60_f225_dev_kit.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__( self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import W25Q64JW from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=W25Q64JW(Codes.READ_1_1_1), with_master=True) # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7) self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32 * 1024 * 1024))
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs): platform = trenz_te0725.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Trenz TE0725 Board", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Use HyperRAM generic PHY as SRAM --------------------------------------------------------- size = int((64 * 1024 * 1024) / 8) hr_pads = platform.request("hyperram", 0) self.submodules.hyperram = HyperRAM(hr_pads) self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), with_led_chaser=True, **kwargs): platform = tinyfpga_bx.Platform() # Disable Integrated ROM since too large for iCE40. kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on TinyFPGA BX", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("clk16")) # SPI Flash -------------------------------------------------------------------------------- from litespi.modules import AT25SF081 from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=AT25SF081(Codes.READ_1_1_1), with_master=False) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( origin = self.mem_map["spiflash"] + bios_flash_offset, size = 32*kB, linker = True) ) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, platform, core_config): # Parameters ------------------------------------------------------------------------------- nrxslots = core_config.get("nrxslots", 2) ntxslots = core_config.get("ntxslots", 2) # PHY -------------------------------------------------------------------------------------- PHYCore.__init__(self, platform, core_config) # MAC -------------------------------------------------------------------------------------- self.submodules.ethmac = ethmac = LiteEthMAC( phy = self.ethphy, dw = 32, interface = "wishbone", endianness = core_config["endianness"], nrxslots = nrxslots, ntxslots = ntxslots, full_memory_we = core_config.get("full_memory_we", False)) # Wishbone Interface ----------------------------------------------------------------------- ethmac_region_size = (nrxslots + ntxslots)*buffer_depth ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) # Interrupt Interface ---------------------------------------------------------------------- self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
def make_soc(self, **kwargs) -> litex_soc.LiteXSoC: soc = super().make_soc(integrated_rom_size=0, integrated_rom_init=[], **kwargs) soc.spiflash_region = SoCRegion(0x00000000, 16 * MB, mode="r", cached=True, linker=True) soc.submodules.spiflash_phy = LiteSPIPHY( soc.platform.request("spiflash"), MX25L12835F(Codes.READ_1_1_1), default_divisor=1) soc.submodules.spiflash_mmap = LiteSPI( phy=soc.spiflash_phy, clk_freq=soc.sys_clk_freq, mmap_endianness=soc.cpu.endianness) soc.csr.add("spiflash_mmap") soc.csr.add("spiflash_phy") soc.bus.add_slave(name="spiflash", slave=soc.spiflash_mmap.bus, region=soc.spiflash_region) soc.bus.add_region("rom", soc.spiflash_region) return soc
def __init__(self, sys_clk_freq=int(100e6), with_vga=False, **kwargs): platform = ego1.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on EGO1 Board", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # VGA terminal ----------------------------------------------------------------------------- if with_vga: self.submodules.terminal = terminal = Terminal() self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000)) vga_pads = platform.request("vga") self.comb += [ vga_pads.vsync.eq(terminal.vsync), vga_pads.hsync.eq(terminal.hsync), vga_pads.red.eq(terminal.red[4:8]), vga_pads.green.eq(terminal.green[4:8]), vga_pads.blue.eq(terminal.blue[4:8]) ] # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1", with_led_chaser=True, **kwargs): platform = tec0117.Platform() # Put BIOS in SPIFlash to save BlockRAMs. kwargs["integrated_rom_size"] = 0 kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on TEC0117", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="4x", dummy_cycles=6) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( origin = self.mem_map["spiflash"] + bios_flash_offset, size = 64*kB, linker = True) ) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: class SDRAMPads: def __init__(self): self.clk = platform.request("O_sdram_clk") self.cke = platform.request("O_sdram_cke") self.cs_n = platform.request("O_sdram_cs_n") self.cas_n = platform.request("O_sdram_cas_n") self.ras_n = platform.request("O_sdram_ras_n") self.we_n = platform.request("O_sdram_wen_n") self.dm = platform.request("O_sdram_dqm") self.a = platform.request("O_sdram_addr") self.ba = platform.request("O_sdram_ba") self.dq = platform.request("IO_sdram_dq") sdram_pads = SDRAMPads() sdram_clk = ClockSignal("sys2x" if sdram_rate == "1:2" else "sys") # FIXME: use phase shift from PLL. self.specials += DDROutput(0, 1, sdram_pads.clk, sdram_clk) sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. l2_cache_size = 128, ) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, platform, spiboot=False, **kwargs): Sim.__init__(self, platform, custom_clocks=local_clocks, spiboot=spiboot, **kwargs) # SoC magic is in here # SHA block -------------------------------------------------------------------------------- self.submodules.sha2 = sha2.Hmac(platform) self.add_csr("sha2") self.add_interrupt("sha2") self.bus.add_slave("sha2", self.sha2.bus, SoCRegion(origin=self.mem_map["sha2"], size=0x4, cached=False))
def __init__(self, sys_clk_freq=int(10e6), with_led_chaser=True, with_gpio_in=True, **kwargs): platform = quicklogic_quickfeather.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["with_uart"] = False if kwargs.get("cpu_type", None) == "eos_s3": kwargs['integrated_sram_size'] = 0 SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QuickLogic QuickFeather", **kwargs) if kwargs.get("cpu_type", None) == "eos_s3": # in fact SRAM starts at 0x2000_0000 - but for some reason # this does not work and most QORC SDK linker scripts # use 0x2002_7000 + 0x0003_c800 self.bus.add_region( "sram", SoCRegion(origin=0x2002_7000, size=0x0003_c800)) self.bus.add_region( "rom", SoCRegion(origin=self.mem_map["rom"], size=4 * 128 * 1024, linker=True)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, with_eos_s3=kwargs["cpu_type"] == "eos_s3") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) # GPIOIn (Interrupt test) ------------------------------------------------------------------ if with_gpio_in: self.submodules.gpio = GPIOIn(platform.request_all("user_btn_n"), with_irq=True) if kwargs["cpu_type"] == "eos_s3": self.irq.add("gpio", use_loc_if_exists=True)
def setup_arena(self, size): region = SoCRegion(self.arena_origin, size, cached=True, linker=True) self.bus.add_region("arena", region) if size > 0: self.submodules.arena = ClockDomainsRenamer("osc")( self.platform.create_ram(32, size, dual_port=True)) self.bus.add_slave("arena_lram", self.arena.bus, region) self.add_config('SOC_SEPARATE_ARENA')
def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, with_led_chaser=False, with_hbm=False, **kwargs): platform = alveo_u280.Platform() if with_hbm: assert 225e6 <= sys_clk_freq <= 450e6 # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Alveo U280 (ES1)", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel, with_hbm) if with_hbm: # JTAGBone -------------------------------------------------------------------------------- self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes. # Add HBM Core. self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(HBMIP(platform)) # Connect four of the HBM's AXI interfaces to the main bus of the SoC. for i in range(4): axi_hbm = hbm.axi[i] axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33) self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm) self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB. else: # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", ddram_channel), memtype = "DDR4", cmd_latency = 1, # seems to work better with cmd_latency=1 sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 600e6, is_rdimm = True) self.add_sdram("sdram", phy = self.ddrphy, module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), size = 0x40000000, l2_cache_size = kwargs.get("l2_size", 8192) ) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("gpio_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_video_terminal=False, **kwargs): platform = muselab_icesugar.Platform() # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs["cpu_variant"] = "lite" kwargs[ "cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Muselab iCESugar", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=64 * kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * kB)) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="1x", dummy_cycles=8) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset, size=32 * kB, linker=True)) # Leds ------------------------------------------------------------------------------------- led_pads = platform.request_all("user_led_n") self.submodules.leds = LedChaser(pads=led_pads, sys_clk_freq=sys_clk_freq)
def setup_rom_in_flash(self): region = SoCRegion(self.spiflash_region.origin + self.rom_offset, self.spiflash_region.size - self.rom_offset, mode='r', cached=True, linker=True) self.bus.add_region("rom", region) self.integrated_rom_initialized = False self.integrated_rom_size = region.size
def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=True, with_mister_vga=False, sdram_rate="1:1", **kwargs): platform = de10nano.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE10-Nano", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if with_mister_sdram and not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) self.add_sdram("sdram", phy=self.sdrphy, module=AS4C32M16(sys_clk_freq, sdram_rate), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # VGA terminal ----------------------------------------------------------------------------- if with_mister_vga: self.submodules.terminal = terminal = Terminal() self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000)) vga_pads = platform.request("vga") self.comb += [ vga_pads.vsync.eq(terminal.vsync), vga_pads.hsync.eq(terminal.hsync), vga_pads.red.eq(terminal.red[2:8]), vga_pads.green.eq(terminal.green[2:8]), vga_pads.blue.eq(terminal.blue[2:8]) ] # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(250e6), with_hbm=False, with_analyzer=False, **kwargs): platform = Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["uart_name"] = "crossover" SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX HBM2 Test SoC on Forest Kitten 33.", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # JTAGBone -------------------------------------------------------------------------------- self.add_jtagbone( chain=2) # Chain 1 already used by HBM2 debug probes. # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(7)]), sys_clk_freq=sys_clk_freq) # HBM -------------------------------------------------------------------------------------- if with_hbm: # Add HBM Core. self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})( HBMIP(platform)) # Connect four of the HBM's AXI interfaces to the main bus of the SoC. for i in range(4): axi_hbm = hbm.axi[i] axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33) self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm) self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000 * i, size=0x1000_0000)) # 256MB. # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ Signal(2), # Add useful signals. Signal(2), # Add useful signals. ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=2048, clock_domain="sys", csr_csv="analyzer.csv")
def addAsyncSram(soc, platform, name, origin, size): ram_bus = wishbone.Interface(data_width=soc.bus.data_width) ram = AsyncSRAM(platform,size) soc.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode="rw")) soc.check_if_exists(name) soc.logger.info("ISSIRAM {} {} {}.".format( colorer(name), colorer("added", color="green"), soc.bus.regions[name])) setattr(soc.submodules, name, ram)
def addCellularRAM(soc, platform, name, origin): size = 16 * 1024 * 1024 ram_bus = wishbone.Interface(data_width=soc.bus.data_width) ram = CellularRAM(soc, platform) soc.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode="rw")) soc.check_if_exists(name) soc.logger.info("CELLULARRAM {} {} {}.".format( colorer(name), colorer("added", color="green"), soc.bus.regions[name])) setattr(soc.submodules, name, ram)
def __init__(self, bios_flash_offset, **kwargs): sys_clk_freq = int(24e6) platform = icebreaker.Platform() platform.add_extension(icebreaker.break_off_pmod) # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 # Set CPU variant / reset address kwargs[ "cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on iCEBreaker", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.submodules.spram = Up5kSPRAM(size=128 * kB) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * kB)) # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="1x", dummy_cycles=8) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region( "rom", SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset, size=32 * kB, linker=True)) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")