def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False, ident_version=True, **kwargs): platform = lpddr4_test_board.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on LPDDR4 Test Board", ident_version = ident_version, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq) # LDDR4 SDRAM ------------------------------------------------------------------------------ if not self.integrated_main_ram_size: self.submodules.ddrphy = lpddr4.K7LPDDR4PHY(platform.request("lpddr4"), iodelay_clk_freq = iodelay_clk_freq, sys_clk_freq = sys_clk_freq, ) self.add_sdram("sdram", phy = self.ddrphy, module = MT53E256M16D1(sys_clk_freq, "1:8"), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = 256, ) # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.register_mem("hyperram", self.mem_map["hyperram"], self.hyperram.bus, 8*1024*1024) # SD Card ---------------------------------------------------------------------------------- if with_sdcard: self.add_sdcard() # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthS7PHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # UartBone --------------------------------------------------------------------------------- if with_uartbone: self.add_uartbone("serial", baudrate=1e6) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False, with_led_chaser=True, **kwargs): platform = lpddr4_test_board.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on LPDDR4 Test Board", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq) # LDDR4 SDRAM ------------------------------------------------------------------------------ if not self.integrated_main_ram_size: self.submodules.ddrphy = lpddr4.K7LPDDR4PHY(platform.request("lpddr4"), iodelay_clk_freq = iodelay_clk_freq, sys_clk_freq = sys_clk_freq, ) self.add_sdram("sdram", phy = self.ddrphy, module = MT53E256M16D1(sys_clk_freq, "1:8"), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = 256, ) # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024)) # SD Card ---------------------------------------------------------------------------------- if with_sdcard: self.add_sdcard() # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: # Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns. # PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns # delay for RX CLK so we only need 0.8ns to match the desired 2ns. self.submodules.ethphy = LiteEthS7PHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), rx_delay = 0.8e-9, ) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # UartBone --------------------------------------------------------------------------------- if with_uartbone: self.add_uartbone("serial", baudrate=1e6) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)