def test_make_pair():
dut = wrap_to_cl(translate(PairTestModel()))
dut.reset()
thing1 = MyType(10, 20)
thing1.w1 = 0b1010101010
thing1.w2 = 0b01010101010101010101
# sets w3 to 00011
thing1.w4 = 0b1111100011
thing2 = MyType(10, 20)
thing2.w1 = ~Bits(10, 0b1010101010)
thing2.w2 = ~Bits(20, 0b01010101010101010101)
# sets w3 to 00011
thing2.w4 = ~Bits(10, 0b1111100011)
result = dut.make_pair(a=thing1, b=thing2)
assert result.pair.first_w1 == thing1.w1
assert result.pair.first_w2 == thing1.w2
assert result.pair.first_w3 == thing1.w3
assert result.pair.first_w4 == thing1.w4
assert result.pair.first == thing1
assert result.pair.second_w1 == thing2.w1
assert result.pair.second_w2 == thing2.w2
assert result.pair.second_w3 == thing2.w3
assert result.pair.second_w4 == thing2.w4
assert result.pair.second == thing2
def test_edge_cases(dividend, divisor, quot, remain, signed):
# Test
N = 64
iface = DivideInterface(N)
div = NonRestoringDivider(iface, N // 2)
div.vcd_file = 'divider.vcd'
dut = wrap_to_cl(div)
dut.reset()
print("{} / {}".format(hex(dividend), hex(divisor)))
print(
dut.div(dividend=Bits(N, dividend),
divisor=Bits(N, divisor),
signed=signed))
for _ in range(64):
dut.cycle()
x = dut.result()
if x != not_ready_instance:
break
dut.cycle()
print(x)
if signed:
assert x.quotient.int() == quot
assert x.rem.int() == remain
else:
assert x.quotient.uint() == quot
assert x.rem.uint() == remain
dut.cycle()
def test_fail3():
iface = MulPipelinedInterface(64)
#mult = MulPipelined(iface, 1)
mult = MulPipelined(iface, 4, use_mul=True)
#mult = MulRetimedPipelined(iface, 4)
mult.vcd_file = 'mult.vcd'
dut = wrap_to_cl(mult)
def peek_tk_mult_cycle(x, tup):
if x is not None:
print(dut.peek().res)
assert dut.peek().res == 0
dut.take()
if tup is not None:
print(tup[0])
dut.mult(src1_signed=tup[0],
src2_signed=tup[0],
src1=tup[1],
src2=tup[2])
dut.cycle()
dut.reset()
peek_tk_mult_cycle(None, (0, 2, 1))
dut.cycle()
dut.cycle()
dut.cycle()
# peek_tk_mult_cycle(None, (0,0,0))
# peek_tk_mult_cycle(None, (0,0,0))
# peek_tk_mult_cycle(None, (0,2,1))
# peek_tk_mult_cycle(0, None)
# peek_tk_mult_cycle(0, None)
# peek_tk_mult_cycle(0, None)
assert dut.peek().res == 2
def test_method(model):
rf = wrap_to_cl(model(8, 4, 1, 1, False, False))
rf.reset()
rf.write(addr=0, data=42)
rf.cycle()
assert rf.read(addr=0).data == 42
def test_method(model):
mux = wrap_to_cl(model(Bits(4), 4))
mux.reset()
result = mux.mux(in_=[0b0001, 0b0010, 0b1000, 0b1000], select=0b00)
assert result.out == 0b0001
mux.cycle()
result = mux.mux(in_=[0b0001, 0b0010, 0b1000, 0b1000], select=0b01)
assert result.out == 0b0010
def test_struct_mux():
mux = wrap_to_cl(translate(Mux(MyType(10, 20), 4)))
mux.reset()
result = mux.mux(in_=[0b0001, 0b0010, 0b1000, 0b1000], select=0b00)
assert result.out == 0b0001
mux.cycle()
result = mux.mux(in_=[0b0001, 0b0010, 0b1000, 0b1000], select=0b01)
assert result.out == 0b0010
def test_bypass_backprop(model):
rf = wrap_to_cl(model(8, 4, 1, 1, False, False))
rf.reset()
rf.write(addr=0, data=42)
rf.cycle()
assert rf.read(addr=0).data == 42
rf.write(addr=0, data=43)
rf.cycle()
def test_struct_decompose():
decomposer = wrap_to_cl(translate(StructTestModel()))
decomposer.reset()
thing = MyType(10, 20)
thing.w1 = 0b1010101010
thing.w2 = 0b01010101010101010101
# sets w3 to 00011
thing.w4 = 0b1111100011
result = decomposer.decompose(thing)
assert result.w1 == thing.w1
assert result.w2 == thing.w2
assert result.w3 == thing.w3
assert result.w4 == thing.w4
def test_basic(): rtl_dut = PipelinedCounter() rtl_dut.vcd_file = 'bob.vcd' dut = wrap_to_cl(translate(rtl_dut)) # dut = wrap_to_cl(rtl_dut) dut.reset() assert isinstance(dut.peek(), NotReady) dut.cycle() assert dut.peek().msg == 2 dut.cycle() assert dut.peek().msg == 2 dut.take() dut.cycle() assert dut.peek().msg == 3
def test_method(model):
freelist = wrap_to_cl(model(4, 2, 1, True, False))
freelist.reset()
alloc = freelist.alloc[0]()
assert alloc.index == 0
assert alloc.mask == 0b0001
freelist.cycle()
alloc = freelist.alloc[1]()
assert alloc.index == 1
assert alloc.mask == 0b0010
freelist.cycle()
alloc1 = freelist.alloc()
alloc2 = freelist.alloc()
freelist.release(0b0011)
assert alloc1.index == 2
assert alloc2.index == 3
assert alloc1.mask == 0b0100
assert alloc2.mask == 0b1000
freelist.cycle()
freelist.free(0b0001)
alloc = freelist.alloc()
assert alloc.index == 0
assert alloc.mask == 0b0001
freelist.cycle()
freelist.reset()
freelist.cycle()
alloc = freelist.alloc[0]()
assert alloc.index == 0
assert alloc.mask == 0b0001
freelist.cycle()
alloc = freelist.alloc[1]()
assert alloc.index == 1
assert alloc.mask == 0b0010
freelist.cycle()
def test_method(model): df = wrap_to_cl(model(DataFlowManagerInterface(64, 32, 64, 4, 2, 2, 1, 4, 1))) df.reset() # simulate add x2, x1, x0 # x2 <- x1 + x0 s1_preg = df.get_src(1) assert s1_preg.preg == 0 s2_preg = df.get_src(0) assert s2_preg.preg == 63 d1_preg = df.get_dst(2) assert d1_preg.preg == 31 s1_read = df.read(s1_preg.preg) assert s1_read.value == 0 s2_read = df.read(s2_preg.preg) assert s2_read.value == 0 df.cycle() df.write(tag=d1_preg.preg, value=0) df.cycle() df.commit(tag=d1_preg.preg, areg=2) df.cycle() # simulate addi x2, x2, 42 s1_preg = df.get_src(2) assert s1_preg.preg == 31 d1_preg = df.get_dst(2) assert d1_preg.preg == 1 s1_read = df.read(s1_preg.preg) assert s1_read.value == 0 df.cycle() df.write(tag=d1_preg.preg, value=42) df.cycle() df.commit(tag=d1_preg.preg, areg=2) df.cycle()
def _create_test_state_machine(rtl_class,
reference_class,
parameters,
argument_strategy={},
translate_model=False,
release_cycle_accuracy=False,
customized_comparators={}):
if isinstance(parameters, dict):
parameters_string = "_".join(
[str(parameter) for parameter in parameters.values()])
model = rtl_class(**parameters)
reference = reference_class(**parameters)
else:
if not isinstance(parameters, tuple):
parameters = (parameters, )
parameters_string = "_".join(
[str(parameter) for parameter in parameters])
model = rtl_class(*parameters)
reference = reference_class(*parameters)
if translate_model:
model = translate(model)
model.vcd_file = "machine.vcd"
sim = wrap_to_cl(model)
Test = type(
type(model).__name__ + "TestStateMachine_" + parameters_string,
TestModel.__bases__, dict(TestModel.__dict__))
Test.interface = None
if type(model.interface) != type(reference.interface):
raise RunMethodTestError(
"Model and reference interface don't match!")
Test.interface = model.interface
for k, v in inspect.getmembers(reference):
precondition = getattr(v, REFERENCE_PRECONDITION_MARKER, None)
if precondition != None:
Test.add_precondition(method_name_fl,
precondition.precondition)
if isinstance(v, MethodStrategy):
for method, strategy in inspect.getmembers(v):
if isinstance(strategy, ArgumentStrategy):
Test.add_argument_strategy(method, strategy.arguments)
for method, arguments in argument_strategy.iteritems():
if isinstance(arguments, ArgumentStrategy):
arguments = arguments.arguments
Test.add_argument_strategy(method, arguments)
if not Test.interface:
raise RunMethodTestError(
"Get rtl model with no interface specified! ")
# make sure that all method arguments have strategy specified
error_msg = """
Found argument with no strategy specified!
- method name : {method_name}
- arg : {arg}
"""
for name, spec in Test.interface.methods.iteritems():
strategies = Test.argument_strategy(name)
for arg, dtype in spec.args.iteritems():
if not strategies.has_key(arg):
strategies[arg] = ArgumentStrategy.get_strategy_from_type(
dtype)
if not strategies[arg]:
raise RunMethodTestError(
error_msg.format(method_name=name, arg=arg))
# add rule
for name, spec in Test.interface.methods.iteritems():
add_rule(Test, spec)
Test.sim = sim
Test.reference = reference
Test.release_cycle_accuracy = release_cycle_accuracy
Test.set_comparators(customized_comparators)
return Test
def run_mem_image(mem_image,
translate,
vcd_file,
max_cycles,
proc2mngr_handler,
trace,
use_cached_verilated=False,
imem_delay=0,
dmem_delay=0):
def tp(thing):
if trace:
print(thing)
initial_mem = {}
mngr2proc_data = deque()
proc2mngr_data = deque()
for name, section in mem_image.iteritems():
to_append = None
if name == '.mngr2proc':
to_append = mngr2proc_data
elif name == '.proc2mngr':
to_append = proc2mngr_data
if to_append is not None:
for i in range(0, len(section.data), XLEN_BYTES):
bits = struct.unpack_from(DATA_PACK_DIRECTIVE,
buffer(section.data, i,
XLEN_BYTES))[0]
to_append.append(Bits(XLEN, bits))
else:
for i, b in enumerate(section.data):
initial_mem[i + section.addr] = b
pth = ProcTestHarness(initial_mem,
mngr2proc_data,
translate,
vcd_file,
use_cached_verilated=use_cached_verilated,
imem_delay=imem_delay,
dmem_delay=dmem_delay)
dut = wrap_to_cl(pth)
curr = 0
i = 0
dut.reset()
tp('')
while True:
assert i < max_cycles
i += 1
tp(
line_block.join([
'{:>5}'.format(i),
Divider(': '),
dut.line_trace(),
]))
tp('')
while len(pth.tdb.received_messages) > curr:
result = proc2mngr_handler(pth.tdb.received_messages[curr],
proc2mngr_data, curr)
if result is not None:
return result
curr += 1
dut.cycle()
def test_functional_form():
dut = wrap_to_cl(translate(FunctionalFormTestModel()))
dut.reset()
assert dut.add_w4(a=0b00001111, b=0b00001001).sum == 0b11111000