class ArmMMU(BaseMMU):
type = 'ArmMMU'
cxx_class = 'gem5::ArmISA::MMU'
cxx_header = 'arch/arm/mmu.hh'
itb = ArmITB()
dtb = ArmDTB()
sys = Param.System(Parent.any, "system object parameter")
stage2_itb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Instruction TLB")
stage2_dtb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Data TLB")
itb_walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
dtb_walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
stage2_itb_walker = Param.ArmTableWalker(ArmStage2TableWalker(),
"HW Table walker")
stage2_dtb_walker = Param.ArmTableWalker(ArmStage2TableWalker(),
"HW Table walker")
@classmethod
def walkerPorts(cls):
return ["mmu.itb_walker.port", "mmu.dtb_walker.port"]
def connectWalkerPorts(self, iport, dport):
self.itb_walker.port = iport
self.dtb_walker.port = dport
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
from m5.objects.ArmTLB import ArmITB, ArmDTB
self.checker = DummyChecker(workload = self.workload)
self.checker.itb = ArmITB(size = self.itb.size)
self.checker.dtb = ArmDTB(size = self.dtb.size)
else:
print("ERROR: Checker only supported under ARM ISA!")
exit(1)
class ArmMMU(BaseMMU):
type = 'ArmMMU'
cxx_class = 'ArmISA::MMU'
cxx_header = 'arch/arm/mmu.hh'
itb = ArmITB()
dtb = ArmDTB()
@classmethod
def walkerPorts(cls):
return ["mmu.itb.walker.port", "mmu.dtb.walker.port"]
def connectWalkerPorts(self, iport, dport):
self.itb.walker.port = iport
self.dtb.walker.port = dport
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
from m5.objects.ArmTLB import ArmDTB, ArmITB
self.checker = O3Checker(workload=self.workload,
exitOnError=False,
updateOnError=True,
warnOnlyOnLoadError=True)
self.checker.itb = ArmITB(size = self.itb.size)
self.checker.dtb = ArmDTB(size = self.dtb.size)
self.checker.cpu_id = self.cpu_id
else:
print("ERROR: Checker only supported under ARM ISA!")
exit(1)