class IdeController(PciDevice):
type = 'IdeController'
cxx_header = "dev/storage/ide_ctrl.hh"
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
VendorID = 0x8086
DeviceID = 0x7111
Command = 0x0
Status = 0x280
Revision = 0x0
ClassCode = 0x01
SubClassCode = 0x01
ProgIF = 0x85
InterruptLine = 0x1f
InterruptPin = 0x01
# Primary
BAR0 = PciIoBar(size='8B')
BAR1 = PciIoBar(size='4B')
# Secondary
BAR2 = PciIoBar(size='8B')
BAR3 = PciIoBar(size='4B')
# DMA
BAR4 = PciIoBar(size='16B')
io_shift = Param.UInt32(0x0, "IO port shift")
ctrl_offset = Param.UInt32(0x0, "IDE disk control offset")
class PciVirtIO(PciDevice):
type = 'PciVirtIO'
cxx_header = 'dev/virtio/pci.hh'
vio = Param.VirtIODeviceBase(VirtIODummyDevice(), "VirtIO device")
VendorID = 0x1AF4
SubsystemVendorID = VendorID
DeviceID = 0x1000
ClassCode = 0xff # Misc device
# The size is overridden by the device model.
BAR0 = PciIoBar(size='4B')
InterruptPin = 0x01 # Use #INTA
class NSGigE(EtherDevBase):
type = 'NSGigE'
cxx_header = "dev/net/ns_gige.hh"
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
VendorID = 0x100B
DeviceID = 0x0022
Status = 0x0290
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
BARs = (PciIoBar(size='256B'), PciMemBar(size='4kB'))
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
InterruptPin = 0x01