def test_coreir_wrap(T): def define_wrap(type_, type_name, in_type): def sim_wrap(self, value_store, state_store): input_val = value_store.get_value(getattr(self, "in")) value_store.set_value(self.out, input_val) return DeclareCircuit( f'coreir_wrap{type_name}', "in", In(in_type), "out", Out(type_), coreir_genargs = {"type": type_}, coreir_name="wrap", coreir_lib="coreir", simulate=sim_wrap ) foo = DefineCircuit("foo", "r", In(T)) EndCircuit() top = DefineCircuit("top", "O", Out(Bit)) foo_inst = foo() wrap = define_wrap(T, "Bit", Bit)() wire(bit(0), wrap.interface.ports["in"]) wire(wrap.out, foo_inst.r) wire(bit(0), top.O) EndCircuit() with tempfile.TemporaryDirectory() as tempdir: filename = f"{tempdir}/top" compile(filename, top, output="coreir") got = open(f"{filename}.json").read() expected_filename = f"tests/test_type/test_coreir_wrap_golden_{T}.json" expected = open(expected_filename).read() assert got == expected
def definition(io): cntreg = DefineRegister(CNTWID, init=0, has_ce=False, has_reset=True, _type=m.UInt) pop_cnt = cntreg(name="pop_cnt") # wire clock m.wireclock(io, pop_cnt) # wire reset m.wire(pop_cnt.RESET, io.rst) # increment enable logic incr_mask = m.bit((pop_cnt.O < m.uint(DEPTH, CNTWID)) & (io.push) & (~io.captured)) wide_incr_mask = repeat(incr_mask, CNTWID) # intermediate signal push_cnt = m.uint(pop_cnt.O + m.uint(m.uint(1, CNTWID) & wide_incr_mask)) # decrement enable logic decr_mask = m.bit((push_cnt > m.uint(0, CNTWID)) & (io.pop)) wide_decr_mask = repeat(decr_mask, CNTWID) # wire next state cnt_update = push_cnt - m.uint(m.uint(1, CNTWID) & wide_decr_mask) m.wire(pop_cnt.I, cnt_update) # wire output m.wire(pop_cnt.O, io.cnt) m.wire(cnt_update, io.next_cnt)
def definition(io): enq_ptr = mantle.Register(address_width) deq_ptr = mantle.Register(address_width) is_full = mantle.FF() do_enq = ~is_full.O & io.enq_val is_empty = ~is_full.O & (enq_ptr.O == deq_ptr.O) do_deq = io.deq_rdy & ~is_empty deq_ptr_inc = m.uint(deq_ptr.O) + 1 enq_ptr_inc = m.uint(enq_ptr.O) + 1 is_full_next = mantle.mux([ mantle.mux([is_full.O, m.bit(False)], do_deq & is_full.O), m.bit(True) ], do_enq & ~do_deq & (enq_ptr_inc == deq_ptr.O)) enq_ptr(mantle.mux([enq_ptr.O, enq_ptr_inc], do_enq)) deq_ptr(mantle.mux([deq_ptr.O, deq_ptr_inc], do_deq)) is_full(is_full_next) ram = mantle.DefineMemory(height, width)() m.wire(ram.RADDR, deq_ptr.O) m.wire(ram.RDATA, io.deq_dat) m.wire(ram.WADDR, enq_ptr.O) m.wire(ram.WDATA, io.enq_dat) m.wire(ram.WE, do_enq) m.wire(io.enq_rdy, ~is_full.O) m.wire(io.deq_val, ~is_empty)
def definition(io): PSEL = getattr(io.apb, f"PSEL{apb_slave_id}") registers = [ mantle.Register(data_width, init=reg.init, has_ce=True, has_reset=True, name=reg.name) for reg in reg_list ] is_write = io.apb.PENABLE & io.apb.PWRITE & PSEL ready = None for i, reg in enumerate(registers): reg.I <= mantle.mux( [getattr(io, reg.name + "_d"), io.apb.PWDATA], is_write) getattr(io, reg.name + "_q") <= reg.O reg.CLK <= io.apb.PCLK reg.RESET <= ~m.bit(io.apb.PRESETn) ce = is_write & (io.apb.PADDR == i) if reg_list[i].has_ce: reg.CE <= ce | m.bit(getattr(io, reg.name + "_en")) else: reg.CE <= ce if ready is not None: ready |= ce else: ready = ce is_read = io.apb.PENABLE & ~io.apb.PWRITE & PSEL io.apb.PREADY <= ready | is_read io.apb.PRDATA <= mantle.mux([reg.O for reg in registers], io.apb.PADDR) io.apb.PSLVERR <= 0 # Unused CorebitTerm().I <= io.apb.PPROT Term(len(io.apb.PSTRB)).I <= io.apb.PSTRB
def logic(a: m.Bit) -> (m.Bit,): if EQ()(a, m.bit(0)): c = m.bit(1) c = m.bit(0) else: c = m.bit(0) c = m.bit(1) return (c,)
def logic(a: m.Bit) -> (m.Bit, m.Bit): d = m.bit(1) if EQ()(a, m.bit(0)): c = m.bit(1) else: c = m.bit(0) d = m.bit(1) return (c, d)
def __init__(self, regs, data_width, apb_slave_id=0): #起名,用到regs的信息 self.name = "RegFile_" + "_".join(reg.name for reg in regs) self.io = io = make_reg_file_interface(regs, data_width, apb_slave_id) for name, port in io.ports.items(): print(f"port_name = \"{name}\"") print(f"port_type = ", end="") m.util.pretty_print_type(type(port)) print() PSEL = getattr(io.apb, f"PSEL{apb_slave_id}") #这里又用了mantle.Register,这个东西能声明成design内部的reg,有五个signal,I,O,CLK,CE,RESET #所以有了后面的reg.I怎么怎么样 registers = [ mantle.Register(data_width, init=reg.init, has_ce=True, has_reset=True, name=reg.name) for reg in regs ] #is_write应该是一个内部的状态 is_write = io.apb.PENABLE & io.apb.PWRITE & PSEL ready = None for i, reg in enumerate(registers): reg.I @= mantle.mux([getattr(io, reg.name + "_d"), io.apb.PWDATA], is_write) getattr(io, reg.name + "_q") <= reg.O reg.CLK @= io.apb.PCLK reg.RESET @= ~m.bit(io.apb.PRESETn) ce = is_write & (io.apb.PADDR == i) if regs[i].has_ce: reg.CE @= ce | m.bit(getattr(io, reg.name + "_en")) else: reg.CE @= ce if ready is not None: ready |= ce else: ready = ce is_read = io.apb.PENABLE & ~io.apb.PWRITE & PSEL io.apb.PREADY @= ready | is_read io.apb.PRDATA @= mantle.mux([reg.O for reg in registers], io.apb.PADDR) io.apb.PSLVERR.undriven() io.apb.PPROT.unused() io.apb.PSTRB.unused()
def txmod_logic( data: m.Bits(8), writing: m.Bit, valid: m.Bit, dataStore: m.Bits(11), writeClock: m.Bits(14), writeBit: m.Bits(4), ) -> ( m.Bit, m.Bits(11), m.Bits(14), m.Bits(4), m.Bit, ): if (writing == m.bit(0)) & (valid == m.bit(1)): writing_out = m.bit(1) dataStore_out = m.concat(dataStore[0:1], data, dataStore[9:]) writeClock_out = m.bits(100, 14) writeBit_out = m.bits(0, 4) TXReg_out = dataStore[0] elif (writing == m.bit(1)) & \ (writeClock == m.bits(0, 14)) & \ (writeBit == m.bits(9, 4)): dataStore_out = dataStore writeClock_out = writeClock writeBit_out = writeBit TXReg_out = m.bit(1) writing_out = m.bit(0) elif (writing == m.bit(1)) & (writeClock == m.bits(0, 14)): writing_out = writing dataStore_out = dataStore TXReg_out = dataStore[writeBit] writeBit_out = m.bits(m.uint(writeBit) + m.bits(1, 4)) writeClock_out = m.bits(100, 14) elif writing == m.bit(1): writing_out = writing dataStore_out = dataStore writeBit_out = writeBit TXReg_out = dataStore[writeBit] writeClock_out = m.bits(m.uint(writeClock) - m.bits(1, 14)) else: writing_out = writing dataStore_out = dataStore writeClock_out = writeClock writeBit_out = writeBit TXReg_out = m.bit(1) return ( writing_out, dataStore_out, writeClock_out, writeBit_out, TXReg_out, )
def NastiReadAddressChannel(nasti_params, id, addr, size, length=0, burst=NastiConstants.BURST_INCR): ar = make_NastiReadAddressChannel(nasti_params)() ar.id @= id ar.addr @= addr ar.length @= length ar.size @= size ar.burst @= burst ar.lock @= m.Bit(0) ar.cache @= NastiConstants.CACHE_DEVICE_NOBUF ar.prot @= NastiConstants.AXPROT(m.bit(0), m.bit(0), m.bit(0)) ar.qos @= m.UInt[4](0b0000) ar.region @= m.UInt[4](0b0000) ar.user @= 0 return ar
def NastiWriteAddressChannel(nasti_params, id, addr, size, length=0, burst=NastiConstants.BURST_INCR): aw = make_NastiWriteAddressChannel(nasti_params)() aw.id @= id aw.addr @= addr aw.length @= length aw.size @= size aw.burst @= burst aw.lock @= m.Bit(0) aw.cache @= NastiConstants.CACHE_DEVICE_NOBUF aw.prot @= NastiConstants.AXPROT(m.bit(0), m.bit(0), m.bit(0)) aw.qos @= m.UInt[4](0b0000) aw.region @= m.UInt[4](0b0000) aw.user @= 0 return aw
def pipeline_logic(): ew_pc.I @= ew_pc.O ew_inst.I @= ew_inst.O ew_alu.I @= ew_alu.O csr_in.I @= csr_in.O st_type.I @= st_type.O ld_type.I @= ld_type.O wb_sel.I @= wb_sel.O wb_en.I @= wb_en.O csr_cmd.I @= csr_cmd.O illegal.I @= illegal.O pc_check.I @= pc_check.O if m.bit(self.io.RESET) | ~stall & csr.expt: st_type.I @= 0 ld_type.I @= 0 wb_en.I @= 0 csr_cmd.I @= 0 illegal.I @= False pc_check.I @= False elif ~stall & ~csr.expt: ew_pc.I @= fe_pc.O ew_inst.I @= fe_inst.O ew_alu.I @= alu.O csr_in.I @= m.mux([rs1, imm_gen.O], self.io.ctrl.imm_sel == IMM_Z) st_type.I @= self.io.ctrl.st_type ld_type.I @= self.io.ctrl.ld_type wb_sel.I @= self.io.ctrl.wb_sel wb_en.I @= self.io.ctrl.wb_en csr_cmd.I @= self.io.ctrl.csr_cmd illegal.I @= self.io.ctrl.illegal pc_check.I @= self.io.ctrl.pc_sel == PC_ALU
def definition(io): config_reg_reset_bit_vector = \ generate_reset_value(constant_bit_count, default_value, reset_val, mux_sel_bit_count) config_cb = mantle.Register(config_reg_width, init=config_reg_reset_bit_vector, has_ce=True, has_async_reset=True) config_addr_zero = m.bits(0, 8) == io.config_addr[24:32] config_cb(io.config_data, CE=m.bit(io.config_en) & config_addr_zero) # if the top 8 bits of config_addr are 0, then read_data is equal # to the value of the config register, otherwise it is 0 m.wire(io.read_data, mantle.mux([m.uint(0, 32), config_cb.O], config_addr_zero)) output_mux = generate_output_mux(num_tracks, feedthrough_outputs, has_constant, width, mux_sel_bit_count, constant_bit_count, io, config_cb) # NOTE: This is a dummy! fix it later! m.wire(output_mux.O, io.out) return
def __init__(self, data_width, data_depth): super().__init__() self.data_width = data_width self.data_depth = data_depth TData = magma.Bits(self.data_width) TBit = magma.Bits(1) self.add_ports(data_in=magma.In(TData), addr_in=magma.In(TData), data_out=magma.Out(TData), clk=magma.In(magma.Clock), config=magma.In(ConfigurationType(8, 32)), read_config_data=magma.Out(magma.Bits(32)), reset=magma.In(magma.AsyncReset), flush=magma.In(TBit), wen_in=magma.In(TBit), ren_in=magma.In(TBit), stall=magma.In(magma.Bits(4))) wrapper = memory_core_genesis2.memory_core_wrapper param_mapping = memory_core_genesis2.param_mapping generator = wrapper.generator(param_mapping, mode="declare") circ = generator(data_width=self.data_width, data_depth=self.data_depth) self.underlying = FromMagma(circ) self.wire(self.ports.data_in, self.underlying.ports.data_in) self.wire(self.ports.addr_in, self.underlying.ports.addr_in) self.wire(self.ports.data_out, self.underlying.ports.data_out) self.wire(self.ports.config.config_addr, self.underlying.ports.config_addr[24:32]) self.wire(self.ports.config.config_data, self.underlying.ports.config_data) self.wire(self.ports.config.write[0], self.underlying.ports.config_en) self.wire(self.underlying.ports.read_data, self.ports.read_config_data) self.wire(self.ports.reset, self.underlying.ports.reset) self.wire(self.ports.flush[0], self.underlying.ports.flush) self.wire(self.ports.wen_in[0], self.underlying.ports.wen_in) self.wire(self.ports.ren_in[0], self.underlying.ports.ren_in) # PE core uses clk_en (essentially active low stall) self.stallInverter = FromMagma(mantle.DefineInvert(1)) self.wire(self.stallInverter.ports.I, self.ports.stall[0:1]) self.wire(self.stallInverter.ports.O[0], self.underlying.ports.clk_en) # TODO(rsetaluri): Actually wire these inputs. signals = ( ("config_en_sram", 4), ("config_en_linebuf", 1), ("chain_wen_in", 1), ("config_read", 1), ("config_write", 1), ("chain_in", self.data_width), ) for name, width in signals: val = magma.bits(0, width) if width > 1 else magma.bit(0) self.wire(Const(val), self.underlying.ports[name]) self.wire(Const(magma.bits(0, 24)), self.underlying.ports.config_addr[0:24])
def definition(io): # didn't work with coreir because the rst/bit conversion # clkEn = io.push | io.pop | m.bit(io.rst) ########################## pointer logic ############################## ptrreg = DefineRegister(PTRWID, init=0, has_ce=True, has_reset=True, _type=m.UInt) wrPtr = ptrreg(name="wrPtr") rdPtr = ptrreg(name="rdPtr") # wire clocks m.wireclock(io, wrPtr) m.wireclock(io, rdPtr) # wire resets m.wire(wrPtr.RESET, io.rst) m.wire(rdPtr.RESET, io.rst) # wire enables m.wire(wrPtr.CE, io.push) m.wire(rdPtr.CE, io.pop) # next values increment by one m.wire(wrPtr.I, wrPtr.O + m.uint(1, PTRWID)) m.wire(rdPtr.I, rdPtr.O + m.uint(1, PTRWID)) ######################### end pointer logic ########################### ######################### full and empty logic ######################## m.wire(io.empty, wrPtr.O == rdPtr.O) m.wire(io.full, (wrPtr.O[1:PTRWID] == rdPtr.O[1:PTRWID]) & (wrPtr.O[0] != rdPtr.O[0])) ######################### end full and empty logic #################### ########################### entry logic ############################### # Create and write entries = [] entryReg = DefineRegister(WIDTH, init=0, has_ce=True, has_reset=False, _type=m.Bits) for i in range(DEPTH): entry = entryReg(name="entry" + str(i)) m.wire( entry.CE, io.push & m.bit(m.uint(wrPtr.O[1:PTRWID]) == m.uint(i, PTRWID - 1))) m.wire(entry.I, io.data_in) entries.append(entry) # Connect mux outmux = Mux(DEPTH, WIDTH) for i in range(DEPTH): m.wire(getattr(outmux, "I" + str(i)), entries[i].O) m.wire(rdPtr.O[1:PTRWID], outmux.S) m.wire(outmux.O, io.data_out)
def wire_reg(reg, reg_input, reg_output=None): m.wire(reg_input, reg.data_in) m.wire(reg.clk, io.CLK) m.wire(reg.reset, io.RESET) m.wire(reg.en, m.bit(1)) if reg_output is not None: m.wire(reg.data_out, reg_output)
def logic(): io.inputMemAddr @= inputStartAddr io.inputMemAddrLen @= 0 # default values required state.I @= state.O inputAddrLineCount.I @= inputAddrLineCount.O inputDataLineCount.I @= inputDataLineCount.O outputState.I @= outputState.O outputWordCounter.I @= outputWordCounter.O if state.O == TopState.inputLengthAddr: if io.inputMemAddrReady: state.I @= TopState.loadInputLength elif state.O == TopState.loadInputLength: if io.inputMemBlockValid: inputLength.I @= io.inputMemBlock[:32] state.I @= TopState.mainLoop elif state.O == TopState.mainLoop: io.inputMemAddr @= m.zext_to(sl(inputAddrLineCount.O, m.bitutils.clog2(bytesInLine)), 64) + \ (inputStartAddr + bytesInLine) # final term is start offset of main data stream remainingAddrLen = inputLength.O - inputAddrLineCount.O - 1 io.inputMemAddrLen @= 63 if remainingAddrLen > 63 else remainingAddrLen[:8] if io.inputMemAddrReady: inputAddrLineCount.I @= inputAddrLineCount.O + 64 if remainingAddrLen > 63 else inputLength.O if io.inputMemBlockValid: inputDataLineCount.I @= inputDataLineCount.O + 1 if inputDataLineCount.O == inputLength.O - 1: state.I @= TopState.pause elif state.O == TopState.pause: # required to flush FeaturePair pipeline before shiftMode is set state.I @= TopState.writeOutput elif state.O == TopState.writeOutput: if outputState.O == OutputState.sendingAddr: if io.outputMemAddrReady: outputState.I @= OutputState.fillingLine elif outputState.O == OutputState.fillingLine: wordInLine = 0 if m.bit(outputWordsInLine == 1) else \ outputWordCounter[:max(1, m.bitutils.clog2(outputWordsInLine))] if m.bit(wordInLine == outputWordsInLine - 1): # TODO figure out why m.bit is needed here outputState.I @= OutputState.sendingLine outputWordCounter.I @= outputWordCounter.O + 1 else: # outputState is sendingLine if io.outputMemBlockReady: if outputWordCounter.O == numOutputWords: state.I @= TopState.finished else: outputState.I @= OutputState.sendingAddr
def definition(io): reg = mantle.Register(n=width, init=0, has_ce=True, has_reset=has_reset) CE = (io.addr == address) & m.bit(io.CE) m.wire(reg(io.I, CE=CE), io.O) if has_reset: m.wire(io.RESET, reg.RESET)
def definition(io): # Instance sram sram = SRAM_512W_16B(name="mem_inst") # Wire up io io.data_out <= sram.Q sram.CLK <= io.clk sram.A <= io.addr sram.D <= io.data_in # Invert control signals # We convert from enable type to bit type to define invert operator # (enables do not have operators by default) sram.CEN <= ~m.bit(io.cen) sram.WEN <= ~m.bit(io.wen) # Set constants sram.EMA <= 0 sram.EMAW <= 0 sram.EMAS <= 0 sram.TEN <= 1 sram.BEN <= 1 sram.RET1N <= 1 sram.STOV <= 0
def test_clock(): assert isinstance(clock(0), ClockType) assert isinstance(clock(1), ClockType) assert isinstance(clock(VCC), ClockType) assert isinstance(clock(GND), ClockType) assert isinstance(clock(bit(0)), ClockType) assert isinstance(clock(clock(0)), ClockType) assert isinstance(clock(reset(0)), ClockType) assert isinstance(clock(enable(0)), ClockType) assert isinstance(clock(bits(0, 1)), ClockType) assert isinstance(clock(uint(0, 1)), ClockType) assert isinstance(clock(sint(0, 1)), ClockType)
def test_reset(): assert isinstance(reset(0), ResetType) assert isinstance(reset(1), ResetType) assert isinstance(reset(VCC), ResetType) assert isinstance(reset(GND), ResetType) assert isinstance(reset(bit(0)), ResetType) assert isinstance(reset(clock(0)), ResetType) assert isinstance(reset(enable(0)), ResetType) assert isinstance(reset(reset(0)), ResetType) assert isinstance(reset(bits(0, 1)), ResetType) assert isinstance(reset(uint(0, 1)), ResetType) assert isinstance(reset(sint(0, 1)), ResetType)
def test_enable(): assert isinstance(enable(0), EnableType) assert isinstance(enable(1), EnableType) assert isinstance(enable(VCC), EnableType) assert isinstance(enable(GND), EnableType) assert isinstance(enable(bit(0)), EnableType) assert isinstance(enable(clock(0)), EnableType) assert isinstance(enable(reset(0)), EnableType) assert isinstance(enable(enable(0)), EnableType) assert isinstance(enable(bits(0, 1)), EnableType) assert isinstance(enable(uint(0, 1)), EnableType) assert isinstance(enable(sint(0, 1)), EnableType)
def state_fsm(): timeout.I @= timeout.O mem_wen1 @= m.bit(False) check_resp_data @= m.bit(False) state.I @= state.O if state.O == TestState.INIT: mem_wen1 @= m.bit(True) if init_counter.COUT: state.I @= TestState.START elif state.O == TestState.START: if gold_req.ready: timeout.I @= m.bits(0, 32) state.I @= TestState.WAIT elif state.O == TestState.WAIT: timeout.I @= timeout.O + 1 if dut.cpu.resp.valid & gold_resp.valid: if ~mask.reduce_or(): check_resp_data @= m.bit(True) state.I @= TestState.DONE elif state.O == TestState.DONE: state.I @= TestState.START
def definition(io): config = mantle.Register(opcode_width, has_ce=True, has_async_reset=True) config_addr_zero = m.bits(0, config_addr_width) == io.config_addr opcode = config(io.config_data, CE=(m.bit(io.config_en) & config_addr_zero)) # TODO: Automatically create instances and wires for configuration # logic. E.g. it could automatically create the register and wire # it up to read_data m.wire(opcode, io.read_data) m.wire(PECore()(opcode, io.I0, io.I1), io.O)
def get_hash_mask(sample_size: SampleSize) -> (m.Bits(4)): if sample_size == SampleSize.ONE_PIXEL: hash_mask = m.repeat(m.bit(0), 4) elif sample_size == SampleSize.HALF_PIXEL: hash_mask = m.concat(m.bit(1), m.repeat(m.bit(0), 3)) elif sample_size == SampleSize.QUARTER_PIXEL: hash_mask = m.concat(m.repeat(m.bit(1), 2), m.repeat(m.bit(0), 2)) else: hash_mask = m.concat(m.repeat(m.bit(1), 3), m.bit(0)) return (hash_mask)
def test_coreir_wrap(T): wrapper = CoreirWrap(T, magma.Bit, "Bit") assert wrapper.out_type == T assert wrapper.in_type == magma.Bit assert wrapper.type_name == "Bit" wrapper_circuit = wrapper.circuit() test_circuit = magma.DefineCircuit("TestCircuit", "O", magma.Out(T)) wrapper_inst = wrapper_circuit() magma.wire(magma.bit(0), wrapper_inst.I) magma.wire(wrapper_inst.O, test_circuit.O) magma.EndCircuit() magma.compile("TEST", test_circuit, output="coreir")
def wire_inst_fields(wrapper_inst, pe_inst, layout): if isinstance(wrapper_inst, m.Product): for key, value in layout.items(): begin = value[0] end = value[1] wire_inst_fields(wrapper_inst[begin:end], getattr(pe_inst, key), value[2]) else: for key, value in layout.items(): begin = value[0] end = value[1] region = wrapper_inst[begin:end] field = getattr(pe_inst, key) if issubclass(type(field), m.Digital): region = m.bit(region) m.wire(region, field)
def __init__(self, x_len: int): self.io = io = m.IO( raddr1=m.In(m.UInt[5]), raddr2=m.In(m.UInt[5]), rdata1=m.Out(m.UInt[x_len]), rdata2=m.Out(m.UInt[x_len]), wen=m.In(m.Enable), waddr=m.In(m.UInt[5]), wdata=m.In(m.UInt[x_len]) ) + m.ClockIO(has_reset=True) regs = RegFileBuilder("reg_file", 32, x_len, write_forward=False, reset_type=m.Reset, backend="verilog") io.rdata1 @= m.mux([0, regs[io.raddr1]], io.raddr1.reduce_or()) io.rdata2 @= m.mux([0, regs[io.raddr2]], io.raddr2.reduce_or()) wen = m.bit(io.wen) & io.waddr.reduce_or() regs.write(io.waddr, io.wdata, enable=m.enable(wen))
def get_hash_mask(sample_size: SampleSize) -> (m.Bits(8)): if sample_size == SampleSize.ONE_PIXEL: hash_mask = m.repeat(m.bit(1), 8) elif sample_size == SampleSize.HALF_PIXEL: hash_mask = m.concat(m.repeat(m.bit(1), 7), m.repeat(m.bit(0), 1)) elif sample_size == SampleSize.QUARTER_PIXEL: hash_mask = m.concat(m.repeat(m.bit(1), 6), m.repeat(m.bit(0), 2)) else: #elif sample_size == SampleSize.EIGHTH_PIXEL: hash_mask = m.concat(m.repeat(m.bit(1), 5), m.repeat(m.bit(0), 3)) return (hash_mask)
def test_const_wire(T, t): foo = DefineCircuit("foo", "I", In(T)) EndCircuit() top = DefineCircuit("top", "O", Out(Bit)) foo_inst = foo() wire(t(0), foo_inst.I) wire(bit(0), top.O) EndCircuit() with tempfile.TemporaryDirectory() as tempdir: filename = f"{tempdir}/top" compile(filename, top, output="coreir") got = open(f"{filename}.json").read() expected_filename = f"tests/test_type/test_const_wire_golden.json" expected = open(expected_filename).read() assert got == expected
def dynamic_mux_select(self, S): if isinstance(S, m.Type): if isinstance(self.T, m._BitKind): length = None else: length = len(self.T) height = len(self) inputs = self.ts[:] if m.mantle_target == "ice40" and height not in [2, 4, 8, 16]: if height > 16: raise NotImplementedError() orig_height = height height = 2**m.bitutils.clog2(height) if not isinstance(inputs[0], m._BitType): raise NotImplementedError(type(inputs[0])) inputs.extend([m.bit(0) for _ in range(height - orig_height)]) return Mux(height, length)(*inputs, S) return orig_get_item(self, S)
def definition(io): rm = RigelMod() m.wire(io.I,rm.process_input) out = rm.process_output+m.uint(10,8) m.wire(io.O,out) m.wire(rm.CE,m.bit(True))