class CounterModM(Circuit):
name = name_
io = IO(**dict(zip(args[::2], args[1::2])))
counter = Counter(n,
cin=cin,
cout=False,
incr=incr,
has_ce=has_ce,
has_reset=True)
reset = Decode(m - 1, n)(counter.O)
if has_reset:
reset = Or(2)(reset, io.RESET)
if has_ce:
CE = io.CE
reset = And(2)(reset, CE)
# reset is sometimes called rollover or RO
# note that we don't return RO in Counter
# should also handle r in the definition
wire(magma.reset(reset), counter.RESET) # synchronous reset
if has_ce:
wire(CE, counter.CE)
if cin:
wire(io.CIN, counter.CIN)
wire(counter.O, io.O)
if cout:
wire(reset, io.COUT)
def test_clock():
assert isinstance(clock(0), ClockType)
assert isinstance(clock(1), ClockType)
assert isinstance(clock(VCC), ClockType)
assert isinstance(clock(GND), ClockType)
assert isinstance(clock(bit(0)), ClockType)
assert isinstance(clock(clock(0)), ClockType)
assert isinstance(clock(reset(0)), ClockType)
assert isinstance(clock(enable(0)), ClockType)
assert isinstance(clock(bits(0, 1)), ClockType)
assert isinstance(clock(uint(0, 1)), ClockType)
assert isinstance(clock(sint(0, 1)), ClockType)
def test_enable():
assert isinstance(enable(0), EnableType)
assert isinstance(enable(1), EnableType)
assert isinstance(enable(VCC), EnableType)
assert isinstance(enable(GND), EnableType)
assert isinstance(enable(bit(0)), EnableType)
assert isinstance(enable(clock(0)), EnableType)
assert isinstance(enable(reset(0)), EnableType)
assert isinstance(enable(enable(0)), EnableType)
assert isinstance(enable(bits(0, 1)), EnableType)
assert isinstance(enable(uint(0, 1)), EnableType)
assert isinstance(enable(sint(0, 1)), EnableType)
def test_bit():
assert isinstance(bit(0), BitType)
assert isinstance(bit(1), BitType)
assert isinstance(bit(VCC), BitType)
assert isinstance(bit(GND), BitType)
assert isinstance(bit(bit(0)), BitType)
assert isinstance(bit(clock(0)), BitType)
assert isinstance(bit(reset(0)), BitType)
assert isinstance(bit(enable(0)), BitType)
assert isinstance(bit(bits(0, 1)), BitType)
assert isinstance(bit(uint(0, 1)), BitType)
assert isinstance(bit(sint(0, 1)), BitType)
class DUT(m.Circuit):
io = m.IO(done=m.Out(m.Bit)) + m.ClockIO(has_reset=True)
core = Core(
x_len, data_path_kwargs=m.generator.ParamDict(ImmGen=ImmGen))()
core.host.fromhost.data.undriven()
core.host.fromhost.valid @= False
# reverse concat because we're using utils with chisel ordering
_hex = [concat(*reversed(x)) for x in loadmem]
imem = RegFileBuilder("imem",
1 << 20,
x_len,
write_forward=False,
reset_type=m.Reset,
backend="verilog")
dmem = RegFileBuilder("dmem",
1 << 20,
x_len,
write_forward=False,
reset_type=m.Reset,
backend="verilog")
INIT, RUN = False, True
state = m.Register(init=INIT)()
cycle = m.Register(m.UInt[32])()
n = len(_hex)
counter = CounterModM(n, n.bit_length(), has_ce=True)
counter.CE @= m.enable(state.O == INIT)
cntr, done = counter.O, counter.COUT
iaddr = (core.icache.req.data.addr // (x_len // 8))[:20]
daddr = (core.dcache.req.data.addr // (x_len // 8))[:20]
dmem_data = dmem[daddr]
imem_data = imem[iaddr]
write = 0
for i in range(x_len // 8):
write |= m.zext_to(
m.mux([dmem_data, core.dcache.req.data.data],
core.dcache.req.valid
& core.dcache.req.data.mask[i])[8 * i:8 * (i + 1)],
32) << (8 * i)
core.RESET @= m.reset(state.O == INIT)
core.icache.resp.valid @= state.O == RUN
core.dcache.resp.valid @= state.O == RUN
core.icache.resp.data.data @= m.Register(
m.UInt[x_len])()(imem_data)
core.dcache.resp.data.data @= m.Register(
m.UInt[x_len])()(dmem_data)
chunk = m.mux(_hex, cntr)
imem.write(m.zext_to(cntr, 20), chunk, m.enable(state.O == INIT))
dmem.write(
m.mux([m.zext_to(cntr, 20), daddr], state.O == INIT),
m.mux([chunk, write], state.O == INIT),
m.enable((state.O == INIT)
| (core.dcache.req.valid
& core.dcache.req.data.mask.reduce_or())))
@m.inline_combinational()
def logic():
state.I @= state.O
cycle.I @= cycle.O
if state.O == INIT:
if done:
state.I @= RUN
if state.O == RUN:
cycle.I @= cycle.O + 1
debug = False
if debug:
m.display("LOADMEM[%x] <= %x", cntr * (x_len // 8),
chunk).when(m.posedge(io.CLK)).if_(state.O == INIT)
m.display("INST[%x] => %x",
iaddr * (x_len // 8), dmem_data).when(
m.posedge(io.CLK)).if_((state.O == RUN)
& core.icache.req.valid)
m.display("MEM[%x] <= %x", daddr * (x_len // 8), write).when(
m.posedge(
io.CLK)).if_((state.O == RUN) & core.dcache.req.valid
& core.dcache.req.data.mask.reduce_or())
m.display(
"MEM[%x] => %x", daddr * (x_len // 8),
dmem_data).when(m.posedge(
io.CLK)).if_((state.O == RUN) & core.dcache.req.valid
& ~core.dcache.req.data.mask.reduce_or())
m.display("cycles: %d", cycle.O).when(m.posedge(
io.CLK)).if_(io.done.value() == 1)
f.assert_immediate(cycle.O < test.maxcycles)
io.done @= core.host.tohost != 0
f.assert_immediate(
(core.host.tohost >> 1) == 0,
failure_msg=("* tohost: %d *", core.host.tohost))
