def test(request, silent=True):
    veriloggen.reset()

    simtype = request.config.getoption('--sim')

    rslt = matrix_reduce_sum.run(
        a_shape,
        axis,
        keep_dims,
        a_dtype,
        b_dtype,
        par,
        axi_datawidth,
        silent,
        filename=None,
        simtype=simtype,
        outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')

    verify_rslt = rslt.splitlines()[-1]
    assert (verify_rslt == '# verify: PASSED')
    rslt = matrix_reduce_sum.run(
        a_shape,
        axis,
        keep_dims,
        a_dtype,
        b_dtype,
        par,
        axi_datawidth,
        silent,
        filename=None,
        simtype=simtype,
        outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')

    verify_rslt = rslt.splitlines()[-1]
    assert (verify_rslt == '# verify: PASSED')


if __name__ == '__main__':
    rslt = matrix_reduce_sum.run(
        a_shape,
        axis,
        keep_dims,
        a_dtype,
        b_dtype,
        par,
        axi_datawidth,
        silent=False,
        filename='tmp.v',
        outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
    print(rslt)