def make_memory_core(): mem_core = MemCore(16, 16, 512, 2, 1) mem_circ = mem_core.circuit() # Setup functional model DATA_DEPTH = 1024 DATA_WIDTH = 16 MemFunctionalModel = gen_memory_core(DATA_WIDTH, DATA_DEPTH) mem_functional_model_inst = MemFunctionalModel() tester = MemoryCoreTester(mem_circ, clock=mem_circ.clk, functional_model=mem_functional_model_inst) tester.poke(mem_circ.reset, 0) tester.step(1) tester.poke(mem_circ.reset, 1) tester.step(1) tester.reset() return [mem_circ, tester, mem_core]
def __init__(self, width, height): super().__init__() self.global_controller = GlobalController(32, 32) columns = [] for i in range(width): tiles = [] for j in range(height): core = MemCore(16, 1024) if (i % 2) else PECore() tiles.append(Tile(core)) columns.append(ColumnMeso(tiles)) self.interconnect = Interconnect(columns) side_type = self.interconnect.side_type self.add_ports( north=magma.Array(width, side_type), south=magma.Array(width, side_type), west=magma.Array(height, side_type), east=magma.Array(height, side_type), jtag=JTAGType, clk_in=magma.In(magma.Clock), reset_in=magma.In(magma.AsyncReset), ) self.wire(self.ports.north, self.interconnect.ports.north) self.wire(self.ports.south, self.interconnect.ports.south) self.wire(self.ports.west, self.interconnect.ports.west) self.wire(self.ports.east, self.interconnect.ports.east) self.wire(self.ports.jtag, self.global_controller.ports.jtag) self.wire(self.ports.clk_in, self.global_controller.ports.clk_in) self.wire(self.ports.reset_in, self.global_controller.ports.reset_in) self.wire(self.global_controller.ports.config, self.interconnect.ports.config) self.wire(self.global_controller.ports.clk_out, self.interconnect.ports.clk) self.wire(self.global_controller.ports.reset_out, self.interconnect.ports.reset) self.wire(self.global_controller.ports.stall, self.interconnect.ports.stall) self.wire(self.interconnect.ports.read_config_data, self.global_controller.ports.read_data_in)
def create_cgra(width: int, height: int, io_sides: IOSide, add_reg: bool = True, mem_ratio: Tuple[int, int] = (1, 4), reg_addr_width: int = 8, config_data_width: int = 32, tile_id_width: int = 16, num_tracks: int = 5, add_pd: bool = True, use_sram_stub: bool = True, hi_lo_tile_id: bool = True, pass_through_clk: bool = True, global_signal_wiring: GlobalSignalWiring = GlobalSignalWiring.Meso, standalone: bool = False, switchbox_type: SwitchBoxType = SwitchBoxType.Imran, port_conn_override: Dict[str, List[Tuple[SwitchBoxSide, SwitchBoxIO]]] = None): # currently only add 16bit io cores bit_widths = [1, 16] track_length = 1 # compute the actual size width, height = get_actual_size(width, height, io_sides) # these values are inclusive x_min, x_max, y_min, y_max = get_array_size(width, height, io_sides) # compute ratio tile_max = mem_ratio[-1] mem_tile_ratio = tile_max - mem_ratio[0] # creates all the cores here # we don't want duplicated cores when snapping into different interconnect # graphs cores = {} for x in range(width): for y in range(height): # empty corner if x in range(x_min) and y in range(y_min): core = None elif x in range(x_min) and y in range(y_max + 1, height): core = None elif x in range(x_max + 1, width) and y in range(y_min): core = None elif x in range(x_max + 1, width) and y in range(y_max + 1, height): core = None elif x in range(x_min) \ or x in range(x_max + 1, width) \ or y in range(y_min) \ or y in range(y_max + 1, height): core = IOCore() else: core = MemCore(use_sram_stub=use_sram_stub) if \ ((x - x_min) % tile_max >= mem_tile_ratio) else \ PeakCore(PE_fc) cores[(x, y)] = core def create_core(xx: int, yy: int): return cores[(xx, yy)] # Specify input and output port connections. inputs = set() outputs = set() for core in cores.values(): # Skip IO cores. if core is None or isinstance(core, IOCore): continue inputs |= {i.qualified_name() for i in core.inputs()} outputs |= {o.qualified_name() for o in core.outputs()} # This is slightly different from the original CGRA. Here we connect # input to every SB_IN and output to every SB_OUT. port_conns = {} in_conn = [(side, SwitchBoxIO.SB_IN) for side in SwitchBoxSide] out_conn = [(side, SwitchBoxIO.SB_OUT) for side in SwitchBoxSide] port_conns.update({input_: in_conn for input_ in inputs}) port_conns.update({output: out_conn for output in outputs}) if port_conn_override is not None: port_conns.update(port_conn_override) pipeline_regs = [] for track in range(num_tracks): for side in SwitchBoxSide: pipeline_regs.append((track, side)) # if reg mode is off, reset to empty if not add_reg: pipeline_regs = [] ics = {} track_list = list(range(num_tracks)) io_in = {"f2io_1": [0], "f2io_16": [0]} io_out = {"io2f_1": track_list, "io2f_16": track_list} for bit_width in bit_widths: if io_sides & IOSide.None_: io_conn = None else: io_conn = {"in": io_in, "out": io_out} ic = create_uniform_interconnect(width, height, bit_width, create_core, port_conns, {track_length: num_tracks}, switchbox_type, pipeline_regs, io_sides=io_sides, io_conn=io_conn) ics[bit_width] = ic interconnect = Interconnect(ics, reg_addr_width, config_data_width, tile_id_width, lift_ports=standalone, stall_signal_width=1) if hi_lo_tile_id: tile_id_physical(interconnect) if add_pd: add_power_domain(interconnect) interconnect.finalize() if global_signal_wiring == GlobalSignalWiring.Meso: apply_global_meso_wiring(interconnect, io_sides=io_sides) elif global_signal_wiring == GlobalSignalWiring.Fanout: apply_global_fanout_wiring(interconnect, io_sides=io_sides) elif global_signal_wiring == GlobalSignalWiring.ParallelMeso: apply_global_meso_wiring(interconnect, io_sides=io_sides) if add_pd: add_aon_read_config_data(interconnect) if pass_through_clk: clk_physical(interconnect) return interconnect
def make_memory_core(): mem_core = MemCore() return mem_core