def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
lambda p: CRG_SE(p, "clk50", None))
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def __init__(self):
XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io,
lambda p: CRG_SE(p, "clk100", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
lambda p: CRG_SE(p, "clk32", None),
_connectors)
def __init__(self):
io, chip = self._io["spartan3a"], "xc3s1400a-ft256-4"
#io, chip = self._io["spartan6"], "xc6slx45-fgg484-2"
XilinxISEPlatform.__init__(
self, chip, io, lambda p: CRG_SE(p, "clk", "rst", 1000 / 32.))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
lambda p: CRG_SE(p, "clk_if", "rst"))
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
lambda p: CRG_SE(p, "clk", "rst", 10.))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: CRG_SE(p, "clk50", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
lambda p: CRG_SE(p, "clk_y3", "user_btn"))
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
def __init__(self):
XilinxISEPlatform.__init__(
self, "xc6slx45-fgg484-2", _io,
lambda p: CRG_SE(p, "clk50", "user_btn", 20.0))