def __init__(self, pads_vga, pads_dvi, lasmim):
pack_factor = lasmim.dw // bpp
g = DataFlowGraph()
self.fi = FrameInitiator(lasmim.aw, pack_factor)
intseq = misc.IntSequence(lasmim.aw, lasmim.aw)
dma_out = AbstractActor(plumbing.Buffer)
g.add_connection(self.fi, intseq, source_subr=self.fi.dma_subr())
g.add_pipeline(intseq, AbstractActor(plumbing.Buffer),
dma_lasmi.Reader(lasmim), dma_out)
cast = structuring.Cast(lasmim.dw,
pixel_layout(pack_factor),
reverse_to=True)
vtg = VTG(pack_factor)
self.driver = Driver(pack_factor, pads_vga, pads_dvi)
g.add_connection(self.fi,
vtg,
source_subr=self.fi.timing_subr,
sink_ep="timing")
g.add_connection(dma_out, cast)
g.add_connection(cast, vtg, sink_ep="pixels")
g.add_connection(vtg, self.driver)
self.submodules += CompositeActor(g)
def __init__(self, pads, asmiport):
self.submodules.edid = EDID(pads)
self.submodules.clocking = Clocking(pads)
invert = False
try:
s = getattr(pads, "data0")
except AttributeError:
s = getattr(pads, "data0_n")
invert = True
self.submodules.data0_cap = DataCapture(8, invert)
self.comb += [
self.data0_cap.pad.eq(s),
self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
]
fifo = RenameClockDomains(AsyncFIFO(10, 256),
{"write": "pix", "read": "sys"})
self.submodules += fifo
self.comb += [
fifo.din.eq(self.data0_cap.d),
fifo.we.eq(1)
]
pack_factor = asmiport.hub.dw//16
self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
self.submodules.dma = spi.DMAWriteController(dma_lasmi.Writer(lasmim), spi.MODE_SINGLE_SHOT)
self.comb += [
self.packer.sink.stb.eq(fifo.readable),
fifo.re.eq(self.packer.sink.ack),
self.packer.sink.word.eq(fifo.dout),
self.packer.source.connect_flat(self.cast.sink),
self.cast.source.connect_flat(self.dma.data)
]
def __init__(self): source = SimSource() sink = SimSink() # A tortuous way of passing integer tokens. packer = structuring.Pack(base_layout, pack_factor) to_raw = structuring.Cast(packed_layout, rawbits_layout) from_raw = structuring.Cast(rawbits_layout, packed_layout) unpacker = structuring.Unpack(pack_factor, base_layout) self.g = DataFlowGraph() self.g.add_connection(source, packer) self.g.add_connection(packer, to_raw) self.g.add_connection(to_raw, from_raw) self.g.add_connection(from_raw, unpacker) self.g.add_connection(unpacker, sink) self.submodules.comp = CompositeActor(self.g) self.submodules.reporter = perftools.DFGReporter(self.g)
def __init__(self, lasmim):
self.sink = sink = stream.Endpoint(user_description(8))
# Pack data
pack_factor = lasmim.dw // 8
pack = structuring.Pack(phy_description(8), pack_factor, reverse=True)
cast = structuring.Cast(pack.source.payload.layout, lasmim.dw)
# DMA
writer = dma_lasmi.Writer(lasmim)
self._reset = CSR()
self.dma = InsertReset(
spi.DMAWriteController(writer, mode=spi.MODE_SINGLE_SHOT))
self.comb += self.dma.reset.eq(self._reset.r & self._reset.re)
# Remove last/length/dst fields from payload
self.comb += [
pack.sink.valid.eq(sink.valid),
pack.sink.payload.eq(sink.payload),
sink.ready.eq(pack.sink.ready)
]
# Graph
g = DataFlowGraph()
g.add_pipeline(pack, cast, self.dma)
self.submodules += CompositeActor(g)
# IRQ
self.submodules.ev = EventManager()
self.ev.done = EventSourcePulse()
self.ev.finalize()
self.comb += self.ev.done.trigger.eq(sink.valid & sink.last)
# CRC
self._crc_failed = CSRStatus()
self.sync += \
If(sink.valid & sink.last,
self._crc_failed.status.eq(sink.error)
)
def __init__(self, lasmim, tag):
self.source = source = Source(user_description(8))
reader = dma_lasmi.Reader(lasmim)
self.dma = spi.DMAReadController(reader, mode=spi.MODE_SINGLE_SHOT)
pack_factor = lasmim.dw // 8
packed_dat = structuring.pack_layout(8, pack_factor)
cast = structuring.Cast(lasmim.dw, packed_dat)
unpack = structuring.Unpack(pack_factor,
phy_description(8),
reverse=True)
# Graph
cnt = Signal(32)
self.sync += \
If(self.dma.generator._shoot.re,
cnt.eq(0)
).Elif(source.stb & source.ack,
cnt.eq(cnt + 1)
)
g = DataFlowGraph()
g.add_pipeline(self.dma, cast, unpack)
self.submodules += CompositeActor(g)
self.comb += [
source.stb.eq(unpack.source.stb),
source.sop.eq(cnt == 0),
source.eop.eq(cnt == (self.dma.length * pack_factor - 1)),
source.length.eq(self.dma.length * pack_factor),
source.data.eq(unpack.source.data),
source.dst.eq(tag),
unpack.source.ack.eq(source.ack)
]
# IRQ
self.submodules.ev = EventManager()
self.ev.done = EventSourcePulse()
self.ev.finalize()
self.comb += self.ev.done.trigger.eq(source.stb & source.eop)