Esempio n. 1
0
	def __init__(self, i, idomain, o, odomain, n):
		self.i = i
		self.idomain = idomain
		self.o = o
		self.odomain = odomain

		w, signed = value_bits_sign(self.i)
		self.regs = [Signal((w, signed)) for i in range(n)]
Esempio n. 2
0
	def emit_verilog(tristate, ns, clock_domains):
		def pe(e):
			return verilog_printexpr(ns, e)[0]
		w, s = value_bits_sign(tristate.target)
		r = "assign " + pe(tristate.target) + " = " \
			+ pe(tristate.oe) + " ? " + pe(tristate.o) \
			+ " : " + str(w) + "'bz;\n"
		if tristate.i is not None:
			r += "assign " + pe(tristate.i) + " = " + pe(tristate.target) + ";\n"
		r += "\n"
		return r
Esempio n. 3
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	def flatten(self, align=False, offset=0, return_offset=False):
		l = []
		for key, alignment in self.field_order:
			if align:
				pad_size = alignment - (offset % alignment)
				if pad_size < alignment:
					l.append(Replicate(0, pad_size))
					offset += pad_size
			
			e = self.__dict__[key]
			if isinstance(e, Signal):
				added = [e]
			elif isinstance(e, Record):
				added = e.flatten(align, offset)
			else:
				raise TypeError
			for x in added:
				offset += value_bits_sign(x)[0]
			l += added
		if return_offset:
			return (l, offset)
		else:
			return l
Esempio n. 4
0
File: misc.py Progetto: vic0/migen 
def bitreverse(s):
	length, signed = value_bits_sign(s)
	l = [s[i] for i in reversed(range(length))]
	return Cat(*l)