def __init__(self): self.s = Signal() myfsm = FSM() self.submodules += myfsm myfsm.act("FOO", self.s.eq(1), NextState("BAR")) myfsm.act("BAR", self.s.eq(0), NextState("FOO")) self.be = myfsm.before_entering("FOO") self.ae = myfsm.after_entering("FOO") self.bl = myfsm.before_leaving("FOO") self.al = myfsm.after_leaving("FOO")
def __init__(self, dw): self.sink = Sink(phy_layout(dw)) self.source = Source(tlp_raw_layout(dw)) ### sink, source = self.sink, self.source sop = Signal() shift = Signal() sink_dat_r = Signal(dw) sink_be_r = Signal(dw // 8) fsm = FSM(reset_state="HEADER1") self.submodules += fsm fsm.act("HEADER1", sink.ack.eq(1), If(sink.stb, shift.eq(1), NextState("HEADER2"))) fsm.act( "HEADER2", sink.ack.eq(1), If( sink.stb, shift.eq(1), If( sink.eop, sink.ack.eq(0), NextState("TERMINATE"), ).Else(NextState("COPY")))) self.sync += [ If(shift, self.source.header.eq(Cat(self.source.header[64:], sink.dat))), If(sink.stb & sink.ack, sink_dat_r.eq(sink.dat), sink_be_r.eq(sink.be)) ] fsm.act( "COPY", sink.ack.eq(source.ack), source.stb.eq(sink.stb), source.sop.eq(sop), source.eop.eq(sink.eop), source.dat.eq( Cat(reverse_bytes(sink_dat_r[32:]), reverse_bytes(sink.dat[:32]))), source.be.eq(Cat(freversed(sink_be_r[4:]), freversed(sink.be[:4]))), If(source.stb & source.ack & source.eop, NextState("HEADER1"))) self.sync += \ If(fsm.before_entering("COPY"), sop.eq(1) ).Elif(source.stb & source.ack, sop.eq(0) ) fsm.act("TERMINATE", sink.ack.eq(source.ack), source.stb.eq(1), source.sop.eq(1), source.eop.eq(1), source.dat.eq(reverse_bytes(sink.dat[32:])), source.be.eq(freversed(sink.be[4:])), If(source.stb & source.ack & source.eop, NextState("HEADER1")))
def __init__(self, sink_description, source_description, header): self.sink = sink = Sink(sink_description) self.source = source = Source(source_description) self.header = Signal(header.length*8) # # # dw = flen(sink.data) header_words = (header.length*8)//dw shift = Signal() counter = Counter(max=max(header_words, 2)) self.submodules += counter if header_words == 1: self.sync += \ If(shift, self.header.eq(sink.data) ) else: self.sync += \ If(shift, self.header.eq(Cat(self.header[dw:], sink.data)) ) fsm = FSM(reset_state="IDLE") self.submodules += fsm if header_words == 1: idle_next_state = "COPY" else: idle_next_state = "RECEIVE_HEADER" fsm.act("IDLE", sink.ack.eq(1), counter.reset.eq(1), If(sink.stb, shift.eq(1), NextState(idle_next_state) ) ) if header_words != 1: fsm.act("RECEIVE_HEADER", sink.ack.eq(1), If(sink.stb, counter.ce.eq(1), shift.eq(1), If(counter.value == header_words-2, NextState("COPY") ) ) ) no_payload = Signal() self.sync += \ If(fsm.before_entering("COPY"), source.sop.eq(1), no_payload.eq(sink.eop) ).Elif(source.stb & source.ack, source.sop.eq(0) ) self.comb += [ source.eop.eq(sink.eop | no_payload), source.data.eq(sink.data), source.error.eq(sink.error), header.decode(self.header, source) ] fsm.act("COPY", sink.ack.eq(source.ack), source.stb.eq(sink.stb | no_payload), If(source.stb & source.ack & source.eop, NextState("IDLE") ) )
def __init__(self, sink_description, source_description, header): self.sink = sink = stream.Endpoint(sink_description) self.source = source = stream.Endpoint(source_description) self.header = Signal(header.length*8) # # # dw = len(sink.data) header_reg = Signal(header.length*8, reset_less=True) header_words = (header.length*8)//dw shift = Signal() counter = Signal(max=max(header_words, 2)) counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) if header_words == 1: self.sync += \ If(shift, header_reg.eq(sink.data) ) else: self.sync += \ If(shift, header_reg.eq(Cat(header_reg[dw:], sink.data)) ) self.comb += self.header.eq(header_reg) fsm = FSM(reset_state="IDLE") self.submodules += fsm if header_words == 1: idle_next_state = "COPY" else: idle_next_state = "RECEIVE_HEADER" fsm.act("IDLE", sink.ready.eq(1), counter_reset.eq(1), If(sink.valid, shift.eq(1), NextState(idle_next_state) ) ) if header_words != 1: fsm.act("RECEIVE_HEADER", sink.ready.eq(1), If(sink.valid, counter_ce.eq(1), shift.eq(1), If(counter == header_words-2, NextState("COPY") ) ) ) no_payload = Signal() self.sync += \ If(fsm.before_entering("COPY"), no_payload.eq(sink.last) ) if hasattr(sink, "error"): self.comb += source.error.eq(sink.error) self.comb += [ source.last.eq(sink.last | no_payload), source.data.eq(sink.data), header.decode(self.header, source) ] fsm.act("COPY", sink.ready.eq(source.ready), source.valid.eq(sink.valid | no_payload), If(source.valid & source.ready & source.last, NextState("IDLE") ) )
def __init__(self, dw): self.sink = Sink(phy_layout(dw)) self.source = Source(tlp_raw_layout(dw)) ### sink, source = self.sink, self.source sop = Signal() shift = Signal() sink_dat_r = Signal(dw) sink_be_r = Signal(dw//8) fsm = FSM(reset_state="HEADER1") self.submodules += fsm fsm.act("HEADER1", sink.ack.eq(1), If(sink.stb, shift.eq(1), NextState("HEADER2") ) ) fsm.act("HEADER2", sink.ack.eq(1), If(sink.stb, shift.eq(1), If(sink.eop, sink.ack.eq(0), NextState("TERMINATE"), ).Else( NextState("COPY") ) ) ) self.sync += [ If(shift, self.source.header.eq(Cat(self.source.header[64:], sink.dat))), If(sink.stb & sink.ack, sink_dat_r.eq(sink.dat), sink_be_r.eq(sink.be) ) ] fsm.act("COPY", sink.ack.eq(source.ack), source.stb.eq(sink.stb), source.sop.eq(sop), source.eop.eq(sink.eop), source.dat.eq(Cat(reverse_bytes(sink_dat_r[32:]), reverse_bytes(sink.dat[:32]))), source.be.eq(Cat(freversed(sink_be_r[4:]), freversed(sink.be[:4]))), If(source.stb & source.ack & source.eop, NextState("HEADER1") ) ) self.sync += \ If(fsm.before_entering("COPY"), sop.eq(1) ).Elif(source.stb & source.ack, sop.eq(0) ) fsm.act("TERMINATE", sink.ack.eq(source.ack), source.stb.eq(1), source.sop.eq(1), source.eop.eq(1), source.dat.eq(reverse_bytes(sink.dat[32:])), source.be.eq(freversed(sink.be[4:])), If(source.stb & source.ack & source.eop, NextState("HEADER1") ) )
def __init__(self, sink_description, source_description, header): self.sink = sink = stream.Endpoint(sink_description) self.source = source = stream.Endpoint(source_description) self.header = Signal(header.length * 8) # # # dw = len(sink.data) header_reg = Signal(header.length * 8, reset_less=True) header_words = (header.length * 8) // dw shift = Signal() counter = Signal(max=max(header_words, 2)) counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) if header_words == 1: self.sync += \ If(shift, header_reg.eq(sink.data) ) else: self.sync += \ If(shift, header_reg.eq(Cat(header_reg[dw:], sink.data)) ) self.comb += self.header.eq(header_reg) fsm = FSM(reset_state="IDLE") self.submodules += fsm if header_words == 1: idle_next_state = "COPY" else: idle_next_state = "RECEIVE_HEADER" fsm.act("IDLE", sink.ready.eq(1), counter_reset.eq(1), If(sink.valid, shift.eq(1), NextState(idle_next_state))) if header_words != 1: fsm.act( "RECEIVE_HEADER", sink.ready.eq(1), If(sink.valid, counter_ce.eq(1), shift.eq(1), If(counter == header_words - 2, NextState("COPY")))) no_payload = Signal() self.sync += \ If(fsm.before_entering("COPY"), no_payload.eq(sink.last) ) if hasattr(sink, "error"): self.comb += source.error.eq(sink.error) self.comb += [ source.last.eq(sink.last | no_payload), source.data.eq(sink.data), header.decode(self.header, source) ] fsm.act( "COPY", sink.ready.eq(source.ready), source.valid.eq(sink.valid | no_payload), If(source.valid & source.ready & source.last, NextState("IDLE")))