# Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """BatchMatMul op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("BatchMatMul") \ .fusion_type("OPAQUE") \ .input(0, "x1") \ .input(1, "x2") \ .output(0, "output") \ .attr("transpose_a", "optional", "bool") \ .attr("transpose_b", "optional", "bool") \ .dtype_format(DT.F16_FracNZ, DT.F16_FracNZ, DT.F16_FracNZ) \ .get_op_info() @op_info_register(op_info) def _batchmatmul_akg(): """BatchMatMul AKG register""" return
# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """RealDiv op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("RealDiv") \ .fusion_type("ELEMWISE") \ .input(0, "x") \ .input(1, "y") \ .output(0, "output") \ .dtype_format(DT.F16_Default, DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.F16_FracNZ, DT.F16_FracNZ, DT.F16_FracNZ) \ .dtype_format(DT.F32_FracNZ, DT.F32_FracNZ, DT.F32_FracNZ) \ .get_op_info() @op_info_register(op_info) def _real_div_akg(): """RealDiv Akg register""" return
# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """Less op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("Less") \ .fusion_type("ELEMWISE") \ .input(0, "x") \ .input(1, "y") \ .output(0, "output") \ .dtype_format(DT.F16_Default, DT.F16_Default, DT.BOOL_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD, DT.BOOL_5HD) \ .get_op_info() @op_info_register(op_info) def _less_akg(): """Less Akg register""" return
# # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """Maximum op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("Maximum") \ .fusion_type("COMMREDUCE") \ .input(0, "x") \ .input(1, "y") \ .output(0, "output") \ .dtype_format(DT.F16_Default, DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.I32_Default, DT.I32_Default, DT.I32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.I32_5HD, DT.I32_5HD, DT.I32_5HD) \ .get_op_info() @op_info_register(op_info) def _maximum_akg(): """Maximum Akg register""" return
# # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """Pow op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("Pow") \ .fusion_type("ELEMWISE") \ .input(0, "x") \ .input(1, "power") \ .output(0, "output") \ .dtype_format(DT.F16_Default, DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.I32_Default, DT.I32_Default, DT.I32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.I32_5HD, DT.I32_5HD, DT.I32_5HD) \ .get_op_info() @op_info_register(op_info) def _power_akg(): """Pow Akg register""" return
# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """ReduceSum op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("ReduceSum") \ .fusion_type("COMMREDUCE") \ .input(0, "x") \ .output(0, "output") \ .attr("axis", "required", "listInt") \ .attr("keep_dims", "required", "bool") \ .attr("atomic_add", "optional", "str") \ .dtype_format(DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.F16_FracNZ, DT.F16_FracNZ) \ .dtype_format(DT.F32_FracNZ, DT.F32_FracNZ) \ .get_op_info() @op_info_register(op_info) def _reduce_sum_akg(): """ReduceSum Akg register""" return
# Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """Reciprocal op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("Reciprocal") \ .fusion_type("ELEMWISE") \ .input(0, "x") \ .output(0, "output") \ .dtype_format(DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD) \ .get_op_info() @op_info_register(op_info) def _reciprocal_akg(): """Reciprocal Akg register""" return
# Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """ReduceMin op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("ReduceMin") \ .fusion_type("COMMREDUCE") \ .input(0, "x") \ .output(0, "output") \ .attr("axis", "required", "listInt") \ .attr("keep_dims", "required", "bool") \ .dtype_format(DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD) \ .get_op_info() @op_info_register(op_info) def _reduce_min_akg(): """ReduceMin Akg register""" return
# you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """ExpandDims op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("ExpandDims") \ .fusion_type("OPAQUE") \ .input(0, "x") \ .output(0, "y") \ .attr("axis", "required", "int") \ .dtype_format(DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.I32_Default, DT.I32_Default) \ .get_op_info() @op_info_register(op_info) def _expand_dims_akg(): """ExpandDims Akg register""" return
# Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """ProdForceSeA op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("ProdForceSeA") \ .fusion_type("ELEMWISE") \ .attr("natoms", "required", "int") \ .input(0, "net_deriv_tensor") \ .input(1, "in_deriv_tensor") \ .input(2, "nlist_tensor") \ .output(0, "output") \ .dtype_format(DT.F32_Default, DT.F32_Default, DT.I32_Default, DT.F32_Default) \ .get_op_info() @op_info_register(op_info) def _prod_force_se_a_akg(): """ProdForceSeA Akg register""" return
# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """AddN op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("AddN") \ .fusion_type("ELEMWISE") \ .input(0, "inputs", "dynamic") \ .output(0, "output") \ .dtype_format(DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.F16_FracZ, DT.F16_FracZ) \ .dtype_format(DT.F32_FracZ, DT.F32_FracZ) \ .dtype_format(DT.F16_FracNZ, DT.F16_FracNZ) \ .dtype_format(DT.F32_FracNZ, DT.F32_FracNZ) \ .get_op_info() @op_info_register(op_info) def _addn_akg(): """AddN Akg register""" return
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """InplaceAssign op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("InplaceAssign") \ .fusion_type("ELEMWISE") \ .input(0, "x") \ .input(1, "y") \ .input(2, "z") \ .output(0, "output") \ .attr("fake_output", "optional", "bool") \ .dtype_format(DT.F16_Default, DT.F16_Default, DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default, DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.I32_Default, DT.I32_Default, DT.I32_Default, DT.I32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD, DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD, DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.I32_5HD, DT.I32_5HD, DT.I32_5HD, DT.I32_5HD) \ .dtype_format(DT.F16_FracZ, DT.F16_FracZ, DT.F16_FracZ, DT.F16_FracZ) \ .dtype_format(DT.F32_FracZ, DT.F32_FracZ, DT.F32_FracZ, DT.F32_FracZ) \ .dtype_format(DT.I32_FracZ, DT.I32_FracZ, DT.I32_FracZ, DT.I32_FracZ) \ .get_op_info() @op_info_register(op_info) def _inplace_assign_akg(): """InplaceAssign Akg register""" return
# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """Select op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("Select") \ .fusion_type("ELEMWISE") \ .input(0, "condition") \ .input(1, "x") \ .input(2, "y") \ .output(0, "output") \ .dtype_format(DT.BOOL_Default, DT.F16_Default, DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.BOOL_Default, DT.F32_Default, DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.BOOL_Default, DT.I32_Default, DT.I32_Default, DT.I32_Default) \ .dtype_format(DT.BOOL_5HD, DT.F16_5HD, DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.BOOL_5HD, DT.F32_5HD, DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.BOOL_5HD, DT.I32_5HD, DT.I32_5HD, DT.I32_5HD) \ .get_op_info() @op_info_register(op_info) def _select_akg(): """Select Akg register""" return
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================ """Mul op""" from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT op_info = AkgAscendRegOp("Mul") \ .fusion_type("ELEMWISE") \ .input(0, "x") \ .input(1, "y") \ .output(0, "output") \ .attr("x_shape", "required", "listInt") \ .attr("y_shape", "required", "listInt") \ .attr("data_format", "required", "listStr") \ .dtype_format(DT.F16_Default, DT.F16_Default, DT.F16_Default) \ .dtype_format(DT.F32_Default, DT.F32_Default, DT.F32_Default) \ .dtype_format(DT.F16_5HD, DT.F16_5HD, DT.F16_5HD) \ .dtype_format(DT.F32_5HD, DT.F32_5HD, DT.F32_5HD) \ .dtype_format(DT.F16_FracZ, DT.F16_FracZ, DT.F16_FracZ) \ .dtype_format(DT.F32_FracZ, DT.F32_FracZ, DT.F32_FracZ) \ .dtype_format(DT.F16_FracNZ, DT.F16_FracNZ, DT.F16_FracNZ) \ .dtype_format(DT.F32_FracNZ, DT.F32_FracNZ, DT.F32_FracNZ) \ .get_op_info() @op_info_register(op_info) def _mul_akg(): """Mul Akg register""" return