def generate_thread_parameters(pipeline_depths, parameters = {}):
thread_count = pipeline_depths["AB_ALU_PIPELINE_DEPTH"]
thread_parameters = {
"THREAD_COUNT" : thread_count,
"THREAD_ADDR_WIDTH" : misc.log2(thread_count)}
parameters_misc.override(thread_parameters, parameters)
return thread_parameters
def generate_common_values(parameters = {}):
common_values = {
"FAMILY" : "Stratix IV",
"DEVICE" : "EP4SE230F29C2",
"CPU_NAME" : "Octavo",
# This normally NEVER changes. If you do change it, update the ALU and decoders to match.
"OPCODE_WIDTH" : 4,
"WORD_WIDTH" : 36,
"MEM_DEPTH" : 1024,
"PORTS_COUNT" : 1,
## Note that the final Verilog output must include double quotes
"MEM_INIT_FILE" : "no_init_file.mem",
## Special case, since never refered again here, so re-quote here
"PC_INIT_FILE" : '"no_init_file.pc"',
## M144Ks are not suitable, and going away in Stratix V.
"MEM_RAMSTYLE" : '"M9K"',
## Thread PC read and write addresses never collide
"PC_RAMSTYLE" : '"MLAB,no_rw_check"'
}
parameters_misc.override(common_values, parameters)
opcode_width = common_values["OPCODE_WIDTH"]
assert opcode_width == 4, "WARNING: You asked for OPCODE_WIDTH of {d}. Do you know what you are doing?".format(opcode_width)
## Address space for each of 3 operands after bits for opcode subtracted. Extra 0, 1, or 2 bits left unused.
addr_width = ((common_values["WORD_WIDTH"] - common_values["OPCODE_WIDTH"]) // 3)
max_mem_depth = 2**addr_width
## By default, include all the memory you can address, unless less specified
if "WORD_WIDTH" in parameters and "MEM_DEPTH" not in parameters:
common_values.update({"MEM_DEPTH":max_mem_depth})
assert common_values["MEM_DEPTH"] <= max_mem_depth, "WARNING: You asked for a MEM_DEPTH of {0}, but you can only address up to {1}".format(common_values["MEM_DEPTH"], max_mem_depth)
common_values.update({
## Bitwise logic uses 3 LSB of opcode
"LOGIC_OPCODE_WIDTH" : (common_values["OPCODE_WIDTH"] - 1),
"ADDR_WIDTH" : addr_width,
"MEM_ADDR_WIDTH" : addr_width,
"PORTS_BASE_ADDR" : (common_values["MEM_DEPTH"] -
common_values["PORTS_COUNT"]),
## Artificially limit minimum I/O address widths to 1 bit. The Verilog uses the port count to handle the discrepancy.
"PORTS_ADDR_WIDTH" : max(1, misc.log2(common_values["PORTS_COUNT"])) })
return common_values
