def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
platform = pipistrello.Platform()
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, # 1.5 MB
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram(self.ddrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
if not self.integrated_rom_size:
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash4x"), dummy=10, div=4,
endianness=self.cpu.endianness, dw=self.cpu_dw)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0x220000
self.register_rom(self.spiflash.bus, 0x1000000)
self.csr_devices.append("spiflash")
def __init__(self,sdram_controller_type="minicon", **kwargs):
platform = metlino.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=125*1000000,
**kwargs)
self.submodules.crg = CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.submodules.ddrphy = kusddrphy.KUSDDRPHY(platform.request("ddram"))
self.config["DDRPHY_WLEVEL"] = None
self.config["KUSDDRPHY"] = None
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
self.csr_devices.append("ddrphy")
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE3", i_GSR=0, i_GTS=0,
i_KEYCLEARB=0, i_PACK=1,
i_USRDONEO=1, i_USRDONETS=1,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0,
i_FCSBO=1, i_FCSBTS=0,
i_DO=0, i_DTS=0b1110)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0x50000
self.register_rom(self.spiflash.bus, 16*1024*1024)
self.csr_devices.append("spiflash")
def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
**kwargs)
self.csr_devices += ["spiflash", "ddrphy"]
self.submodules.crg = _CRG(platform)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus, 16*1024*1024)
def __init__(self, sdram_controller_type="minicon", **kwargs):
platform = kasli.Platform()
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 2.5 [current_design]",
])
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0x400000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.clk_freq)
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
self.csr_devices.append("ddrphy")
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash2x")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=5, div=2)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0x450000
self.register_rom(self.spiflash.bus, 16*1024*1024)
self.csr_devices.append("spiflash")
def __init__(self, **kwargs):
platform = papilio_pro.Platform()
clk_freq = 80 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_reset_address=0x60000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon", sdram_module.geom_settings,
sdram_module.timing_settings)
if not self.integrated_rom_size:
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash2x"),
dummy=4,
div=6,
endianness=self.cpu.endianness,
dw=self.cpu_dw)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
self.csr_devices.append("spiflash")
def __init__(self,
sdram_controller_type="minicon",
with_spiflash=False,
**kwargs):
platform = afc3v1.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=125000000, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.)
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J512M8(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.csr_devices.append("ddrphy")
self.submodules.si570_oen = gpio.GPIOIn(platform.request(
"si570_en", 0))
self.csr_devices.append("si570_oen")
if not self.integrated_rom_size or with_spiflash:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads,
dummy=11,
div=2,
endianness=self.cpu.endianness,
dw=self.cpu_dw)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.csr_devices.append("spiflash")
if with_spiflash:
self.add_wb_slave(self.mem_map["spiflash"], 16 * 1024 * 1024,
self.spiflash.bus)
if not self.integrated_rom_size:
self.flash_boot_address = 0x350000
self.register_rom(self.spiflash.bus, 16 * 1024 * 1024)
def __init__(self,
sdram_controller_type="minicon",
hw_rev="v1.0",
**kwargs):
platform = kasli.Platform(hw_rev=hw_rev)
SoCSDRAM.__init__(self,
platform,
clk_freq=125e6 * 15.25 / 16,
cpu_reset_address=0x400000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / self.clk_freq)
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.csr_devices.append("ddrphy")
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash2x")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads,
dummy=5,
div=2)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0x450000
self.register_rom(self.spiflash.bus, 16 * 1024 * 1024)
self.csr_devices.append("spiflash")
def __init__(self, **kwargs):
platform = qm_xc6slx16_sdram.Platform()
clk_freq = 80 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x5000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC16M16(clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon", sdram_module.geom_settings,
sdram_module.timing_settings)
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash"), dummy=8, div=2)
self.register_mem("spiflash", 0x70000000, 0x1000000, self.spiflash.bus)
self.flash_boot_address = 0x70080000
def __init__(self, sdram_controller_type="minicon", hw_rev=None, **kwargs):
if hw_rev is None:
hw_rev = "v1.0"
platform = kasli.Platform(hw_rev=hw_rev)
platform.add_extension(virtual_platform._io)
SoCSDRAM.__init__(self,
platform,
clk_freq=125e6 * 14.5 / 16,
cpu_reset_address=0x400000,
**kwargs)
self.remove_subsystem_by_type("MOR1KX")
self.submodules.cpu = bridge_cpu = BridgeCPU(platform=platform)
self.add_wb_master(bridge_cpu.dbus)
self.config["HW_REV"] = hw_rev
self.submodules.crg = _KasliCRG(platform)
self.submodules.ddrphy = BridgeDFI(
pads=self.platform.request("virt_ddr"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.csr_devices.append("ddrphy")
if not self.integrated_rom_size:
spiflash_pads = self.platform.request("virt_spiflash")
spiflash_dummy_clks = 3
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy_clks, div=2)
self.config["SPIFLASH_DUMMY_CLKS"] = spiflash_dummy_clks
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0xb40000
self.register_rom(self.spiflash.bus, 16 * 1024 * 1024)
self.csr_devices.append("spiflash")
