Esempio n. 1
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    def __init__(self, **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="or1k",
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         ident=artiq_version,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
            self.platform.toolchain.bitstream_commands.extend([
                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
            ])
        if isinstance(self.platform.toolchain, XilinxISEToolchain):
            self.platform.toolchain.bitgen_opt += " -g compress"

        self.submodules.leds = gpio.GPIOOut(Cat(
            self.platform.request("user_led", 0),
            self.platform.request("user_led", 1)))
        self.csr_devices.append("leds")

        self.platform.add_extension(_sma33_io)
        self.platform.add_extension(_ams101_dac)
        self.platform.add_extension(_sdcard_spi_33)
        self.platform.add_extension(_zotino)
        self.platform.add_extension(_urukul)

        i2c = self.platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.csr_devices.append("i2c")
        self.config["I2C_BUS_COUNT"] = 1

        self.config["HAS_DDS"] = None
Esempio n. 2
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    def __init__(self, cpu_type="or1k", **kwargs):
        MiniSoC.__init__(self,
                         cpu_type=cpu_type,
                         sdram_controller_type="minicon",
                         l2_size=128 * 1024,
                         ident=artiq_version,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
            self.platform.toolchain.bitstream_commands.extend([
                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
            ])
        if isinstance(self.platform.toolchain, XilinxISEToolchain):
            self.platform.toolchain.bitgen_opt += " -g compress"

        self.submodules.leds = gpio.GPIOOut(
            Cat(self.platform.request("user_led", 0),
                self.platform.request("user_led", 1)))
        self.csr_devices.append("leds")

        self.platform.add_extension(_sma33_io)
        self.platform.add_extension(_ams101_dac)

        i2c = self.platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.csr_devices.append("i2c")
        self.config["I2C_BUS_COUNT"] = 1

        self.config["HAS_DDS"] = None
Esempio n. 3
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    def __init__(self, cpu_type="or1k", **kwargs):
        MiniSoC.__init__(self,
                         cpu_type=cpu_type,
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         with_timer=False,
                         ident=artiq_version,
                         **kwargs)
        AMPSoC.__init__(self)
        if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
            self.platform.toolchain.bitstream_commands.extend([
                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
            ])
        if isinstance(self.platform.toolchain, XilinxISEToolchain):
            self.platform.toolchain.bitgen_opt += " -g compress"

        self.submodules.leds = gpio.GPIOOut(Cat(
            self.platform.request("user_led", 0),
            self.platform.request("user_led", 1)))

        self.platform.add_extension(_ams101_dac)

        i2c = self.platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.register_kernel_cpu_csrdevice("i2c")
        self.config["I2C_BUS_COUNT"] = 1
Esempio n. 4
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    def __init__(self, cpu_type="or1k", **kwargs):
        MiniSoC.__init__(self,
                         cpu_type=cpu_type,
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         with_timer=False,
                         ident=artiq_version,
                         **kwargs)
        AMPSoC.__init__(self)

        self.submodules.leds = gpio.GPIOOut(Cat(
            self.platform.request("user_led", 0),
            self.platform.request("user_led", 1)))
Esempio n. 5
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    def __init__(self, cpu_type="or1k", **kwargs):
        MiniSoC.__init__(self,
                         cpu_type=cpu_type,
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         with_timer=False,
                         ident=artiq_version,
                         **kwargs)
        AMPSoC.__init__(self)
        if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
            self.platform.toolchain.bitstream_commands.extend([
                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
            ])
        if isinstance(self.platform.toolchain, XilinxISEToolchain):
            self.platform.toolchain.bitgen_opt += " -g compress"

        self.submodules.leds = gpio.GPIOOut(Cat(
            self.platform.request("user_led", 0),
            self.platform.request("user_led", 1)))
Esempio n. 6
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    def __init__(self,
                 gateware_identifier_str=None,
                 drtio_100mhz=False,
                 **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="vexriscv",
                         cpu_bus_width=64,
                         sdram_controller_type="minicon",
                         l2_size=128 * 1024,
                         integrated_sram_size=8192,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        add_identifier(self, gateware_identifier_str=gateware_identifier_str)

        if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
            self.platform.toolchain.bitstream_commands.extend([
                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
            ])
        if isinstance(self.platform.toolchain, XilinxISEToolchain):
            self.platform.toolchain.bitgen_opt += " -g compress"

        self.submodules.timer1 = timer.Timer()
        self.csr_devices.append("timer1")
        self.interrupt_devices.append("timer1")

        self.submodules.leds = gpio.GPIOOut(
            Cat(self.platform.request("user_led", 0),
                self.platform.request("user_led", 1)))
        self.csr_devices.append("leds")

        self.platform.add_extension(_reprogrammed3v3_io)
        self.platform.add_extension(_ams101_dac)

        i2c = self.platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.csr_devices.append("i2c")
        self.config["I2C_BUS_COUNT"] = 1

        self.config["HAS_DDS"] = None
Esempio n. 7
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    def __init__(self, **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="or1k",
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         ident=artiq_version,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)

        platform = self.platform

        self.comb += platform.request("sfp_tx_disable_n").eq(1)
        tx_pads = platform.request("sfp_tx")
        rx_pads = platform.request("sfp_rx")

        # 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
        self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
            clock_pads=platform.request("sgmii_clock"),
            tx_pads=tx_pads,
            rx_pads=rx_pads,
            sys_clk_freq=self.clk_freq,
            clock_div2=True)

        self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
            DRTIOMaster(self.transceiver.channels[0]))
        self.csr_devices.append("drtio0")
        self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
                          self.drtio0.aux_controller.bus)
        self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
        self.config["HAS_DRTIO"] = None
        self.add_csr_group("drtio", ["drtio0"])
        self.add_memory_group("drtio_aux", ["drtio0_aux"])

        platform.add_extension(ad9154_fmc_ebz)
        ad9154_spi = platform.request("ad9154_spi")
        self.comb += ad9154_spi.en.eq(1)
        self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
        self.csr_devices.append("converter_spi")

        self.comb += [
            platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
            platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
        ]

        rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
        platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
        platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
        platform.add_false_path_constraints(
            self.crg.cd_sys.clk,
            self.transceiver.txoutclk, self.transceiver.rxoutclk)

        rtio_channels = []
        for i in range(8):
            phy = ttl_simple.Output(platform.request("user_led", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        for sma in "user_sma_gpio_p", "user_sma_gpio_n":
            phy = ttl_simple.InOut(platform.request(sma))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))

        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
        self.csr_devices.append("rtio_moninj")

        self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
        self.csr_devices.append("rtio_core")

        self.submodules.rtio = rtio.KernelInitiator()
        self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
            rtio.DMA(self.get_native_sdram_if()))
        self.register_kernel_cpu_csrdevice("rtio")
        self.register_kernel_cpu_csrdevice("rtio_dma")
        self.submodules.cri_con = rtio.CRIInterconnectShared(
            [self.rtio.cri, self.rtio_dma.cri],
            [self.rtio_core.cri, self.drtio0.cri])
        self.register_kernel_cpu_csrdevice("cri_con")
Esempio n. 8
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    def __init__(self, cpu_type="or1k", **kwargs):
        MiniSoC.__init__(self,
                         cpu_type=cpu_type,
                         sdram_controller_type="minicon",
                         l2_size=128 * 1024,
                         ident=artiq_version,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        self.platform.toolchain.bitstream_commands.extend([
            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
        ])

        platform = self.platform
        platform.add_extension(ad9154_fmc_ebz)

        self.submodules.leds = gpio.GPIOOut(
            Cat(platform.request("user_led", 0),
                platform.request("user_led", 1)))
        self.csr_devices.append("leds")

        i2c = platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.csr_devices.append("i2c")
        self.config["I2C_BUS_COUNT"] = 1

        ad9154_spi = platform.request("ad9154_spi")
        self.comb += ad9154_spi.en.eq(1)
        self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
        self.csr_devices.append("converter_spi")
        self.config["CONVERTER_SPI_DAC_CS"] = 0
        self.config["CONVERTER_SPI_CLK_CS"] = 1
        self.config["HAS_AD9516"] = None

        self.submodules.ad9154 = AD9154(platform)
        self.csr_devices.append("ad9154")

        rtio_channels = []

        phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))

        phy = ttl_simple.Output(platform.request("user_led", 2))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy))

        sysref_pads = platform.request("ad9154_sysref")
        phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
        self.submodules += phy
        rtio_channels.append(
            rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=2))

        self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)

        self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
        rtio_channels.extend(
            rtio.Channel.from_phy(phy) for sawg in self.ad9154.sawgs
            for phy in sawg.phys)

        self.config["HAS_RTIO_LOG"] = None
        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
        rtio_channels.append(rtio.LogChannel())

        self.submodules.rtio_crg = _PhaserCRG(platform,
                                              self.ad9154.jesd.cd_jesd.clk)
        self.csr_devices.append("rtio_crg")
        self.submodules.rtio_core = rtio.Core(rtio_channels)
        self.csr_devices.append("rtio_core")
        self.submodules.rtio = rtio.KernelInitiator()
        # self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
        self.register_kernel_cpu_csrdevice("rtio")
        # self.register_kernel_cpu_csrdevice("rtio_dma")
        self.submodules.cri_con = rtio.CRIInterconnectShared(
            [self.rtio.cri],  # , self.rtio_dma.cri],
            [self.rtio_core.cri])
        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
        self.csr_devices.append("rtio_moninj")
        self.submodules.rtio_analyzer = rtio.Analyzer(
            self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
        self.csr_devices.append("rtio_analyzer")

        platform.add_false_path_constraints(self.crg.cd_sys.clk,
                                            self.rtio_crg.cd_rtio.clk)
        platform.add_false_path_constraints(self.crg.cd_sys.clk,
                                            self.ad9154.jesd.cd_jesd.clk)
        for phy in self.ad9154.jesd.phys:
            platform.add_false_path_constraints(self.crg.cd_sys.clk,
                                                phy.gtx.cd_tx.clk)
Esempio n. 9
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    def __init__(self, cfg, **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="or1k",
                         sdram_controller_type="minicon",
                         l2_size=128 * 1024,
                         ident=artiq_version,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)

        platform = self.platform

        self.comb += platform.request("sfp_tx_disable_n").eq(1)
        tx_pads = platform.request("sfp_tx")
        rx_pads = platform.request("sfp_rx")
        if cfg == "simple_gbe":
            # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
            # simple TTLs
            self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
                clock_pads=platform.request("sgmii_clock"),
                tx_pads=tx_pads,
                rx_pads=rx_pads,
                sys_clk_freq=self.clk_freq,
                clock_div2=True)
        elif cfg == "sawg_3g":
            # 3Gb link, 150MHz RTIO clock
            # with SAWG on local RTIO and AD9154-FMC-EBZ
            platform.add_extension(ad9154_fmc_ebz)
            self.submodules.transceiver = gtx_7series.GTX_3G(
                clock_pads=platform.request("ad9154_refclk"),
                tx_pads=tx_pads,
                rx_pads=rx_pads,
                sys_clk_freq=self.clk_freq)

            ad9154_spi = platform.request("ad9154_spi")
            self.comb += ad9154_spi.en.eq(1)
            self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
            self.csr_devices.append("converter_spi")
            self.config["CONVERTER_SPI_DAC_CS"] = 0
            self.config["CONVERTER_SPI_CLK_CS"] = 1
            self.config["HAS_AD9516"] = None
        else:
            raise ValueError
        self.submodules.drtio = DRTIOMaster(self.transceiver)
        self.csr_devices.append("drtio")
        self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
                          self.drtio.aux_controller.bus)
        self.add_memory_region("drtio_aux",
                               self.mem_map["drtio_aux"] | self.shadow_base,
                               0x800)

        self.comb += [
            platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
            platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
        ]

        rtio_clk_period = 1e9 / self.transceiver.rtio_clk_freq
        platform.add_period_constraint(self.transceiver.txoutclk,
                                       rtio_clk_period)
        platform.add_period_constraint(self.transceiver.rxoutclk,
                                       rtio_clk_period)
        platform.add_false_path_constraints(self.crg.cd_sys.clk,
                                            self.transceiver.txoutclk,
                                            self.transceiver.rxoutclk)

        rtio_channels = []
        for i in range(8):
            phy = ttl_simple.Output(platform.request("user_led", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        for sma in "user_sma_gpio_p", "user_sma_gpio_n":
            phy = ttl_simple.Inout(platform.request(sma))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
        self.csr_devices.append("rtio_core")

        self.submodules.rtio = rtio.KernelInitiator()
        self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
        self.register_kernel_cpu_csrdevice("rtio")
        self.register_kernel_cpu_csrdevice("rtio_dma")
        self.submodules.cri_con = rtio.CRIInterconnectShared(
            [self.rtio.cri, self.rtio_dma.cri],
            [self.drtio.cri, self.rtio_core.cri])
    def __init__(self, **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="or1k",
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         with_timer=False,
                         ident="DRTIO_DEMO",
                         **kwargs)
        AMPSoC.__init__(self)

        platform = self.platform
        platform.add_extension(ttl_extension)

        rtio_channels = []
        phy = ttl_simple.Output(platform.request("user_sma_gpio_p"))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy))
        phy = ttl_simple.Output(platform.request("user_sma_gpio_n"))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy))
        for i in range(8):
            phy = ttl_simple.Output(platform.request("user_led"))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        for i in range(22):
            phy = ttl_simple.Output(platform.request("ttl"))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        self.comb += platform.request("sfp_tx_disable_n").eq(1)
        self.submodules.remote_ttl_channels = RemoteTTLChannels(
            clock_pads=platform.request("sgmii_clock"),
            tx_pads=platform.request("sfp_tx"),
            sys_clk_freq=125000000)
        rtio_channels += self.remote_ttl_channels.rtio_channels
        self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
        rtio_channels.append(rtio.LogChannel())

        sma = platform.request("user_sma_clock_p")
        self.comb += sma.eq(ClockSignal("tx"))

        self.submodules.rtio = rtio.RTIO(rtio_channels)
        self.register_kernel_cpu_csrdevice("rtio")
        self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)

        self.specials += [
            Keep(self.rtio.cd_rsys.clk),
            Keep(self.remote_ttl_channels.cd_rtio.clk),
            Keep(self.ethphy.crg.cd_eth_rx.clk),
            Keep(self.ethphy.crg.cd_eth_tx.clk),
        ]

        platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)
        platform.add_period_constraint(self.remote_ttl_channels.cd_rtio.clk, 16.)
        platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
        platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
        platform.add_false_path_constraints(
            self.rtio.cd_rsys.clk,
            self.remote_ttl_channels.cd_rtio.clk,
            self.ethphy.crg.cd_eth_rx.clk,
            self.ethphy.crg.cd_eth_tx.clk)

        self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
            self.get_native_sdram_if())
Esempio n. 11
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    def __init__(self, gateware_identifier_str=None, **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="vexriscv",
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         integrated_sram_size=8192,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        add_identifier(self, gateware_identifier_str=gateware_identifier_str)

        if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
            self.platform.toolchain.bitstream_commands.extend([
                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
            ])
        if isinstance(self.platform.toolchain, XilinxISEToolchain):
            self.platform.toolchain.bitgen_opt += " -g compress"

        platform = self.platform
        platform.add_extension(_reprogrammed3v3_io)
        platform.add_extension(_ams101_dac)

        self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
        data_pads = [
            platform.request("sfp"), platform.request("user_sma_mgt")
        ]

        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
        self.submodules.drtio_transceiver = gtx_7series.GTX(
            clock_pads=platform.request("si5324_clkout"),
            pads=data_pads,
            sys_clk_freq=self.clk_freq)
        self.csr_devices.append("drtio_transceiver")

        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)

        drtio_csr_group = []
        drtioaux_csr_group = []
        drtioaux_memory_group = []
        self.drtio_cri = []
        for i in range(len(self.drtio_transceiver.channels)):
            core_name = "drtio" + str(i)
            coreaux_name = "drtioaux" + str(i)
            memory_name = "drtioaux" + str(i) + "_mem"
            drtio_csr_group.append(core_name)
            drtioaux_csr_group.append(coreaux_name)
            drtioaux_memory_group.append(memory_name)

            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})

            core = cdr(DRTIOMaster(
                self.rtio_tsc, self.drtio_transceiver.channels[i]))
            setattr(self.submodules, core_name, core)
            self.drtio_cri.append(core.cri)
            self.csr_devices.append(core_name)

            coreaux = cdr(DRTIOAuxController(core.link_layer))
            setattr(self.submodules, coreaux_name, coreaux)
            self.csr_devices.append(coreaux_name)

            memory_address = self.mem_map["drtioaux"] + 0x800*i
            self.add_wb_slave(memory_address, 0x800,
                              coreaux.bus)
            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
        self.config["HAS_DRTIO"] = None
        self.config["HAS_DRTIO_ROUTING"] = None
        self.add_csr_group("drtio", drtio_csr_group)
        self.add_csr_group("drtioaux", drtioaux_csr_group)
        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)

        self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
        self.csr_devices.append("si5324_rst_n")
        i2c = self.platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.csr_devices.append("i2c")
        self.config["I2C_BUS_COUNT"] = 1
        self.config["HAS_SI5324"] = None
        self.config["SI5324_AS_SYNTHESIZER"] = None

        self.comb += [
            platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
            platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
        ]

        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
        # Constrain TX & RX timing for the first transceiver channel
        # (First channel acts as master for phase alignment for all channels' TX)
        gtx0 = self.drtio_transceiver.gtxs[0]
        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
        platform.add_false_path_constraints(
            self.crg.cd_sys.clk,
            gtx0.txoutclk, gtx0.rxoutclk)
        # Constrain RX timing for the each transceiver channel
        # (Each channel performs single-lane phase alignment for RX)
        for gtx in self.drtio_transceiver.gtxs[1:]:
            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
            platform.add_false_path_constraints(
                self.crg.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)

        self.submodules.rtio_crg = _RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
        self.csr_devices.append("rtio_crg")
        fix_serdes_timing_path(platform)
Esempio n. 12
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    def __init__(self, gateware_identifier_str=None, **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="or1k",
                         sdram_controller_type="minicon",
                         l2_size=128 * 1024,
                         integrated_sram_size=8192,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        add_identifier(self, gateware_identifier_str=gateware_identifier_str)

        if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
            self.platform.toolchain.bitstream_commands.extend([
                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
            ])
        if isinstance(self.platform.toolchain, XilinxISEToolchain):
            self.platform.toolchain.bitgen_opt += " -g compress"

        platform = self.platform

        self.comb += platform.request("sfp_tx_disable_n").eq(1)
        tx_pads = [
            platform.request("sfp_tx"),
            platform.request("user_sma_mgt_tx")
        ]
        rx_pads = [
            platform.request("sfp_rx"),
            platform.request("user_sma_mgt_rx")
        ]

        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
        self.submodules.drtio_transceiver = gtx_7series.GTX(
            clock_pads=platform.request("si5324_clkout"),
            tx_pads=tx_pads,
            rx_pads=rx_pads,
            sys_clk_freq=self.clk_freq)
        self.csr_devices.append("drtio_transceiver")

        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)

        drtio_csr_group = []
        drtioaux_csr_group = []
        drtioaux_memory_group = []
        drtio_cri = []
        for i in range(len(self.drtio_transceiver.channels)):
            core_name = "drtio" + str(i)
            coreaux_name = "drtioaux" + str(i)
            memory_name = "drtioaux" + str(i) + "_mem"
            drtio_csr_group.append(core_name)
            drtioaux_csr_group.append(coreaux_name)
            drtioaux_memory_group.append(memory_name)

            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})

            core = cdr(
                DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
            setattr(self.submodules, core_name, core)
            drtio_cri.append(core.cri)
            self.csr_devices.append(core_name)

            coreaux = cdr(DRTIOAuxController(core.link_layer))
            setattr(self.submodules, coreaux_name, coreaux)
            self.csr_devices.append(coreaux_name)

            memory_address = self.mem_map["drtioaux"] + 0x800 * i
            self.add_wb_slave(memory_address, 0x800, coreaux.bus)
            self.add_memory_region(memory_name,
                                   memory_address | self.shadow_base, 0x800)
        self.config["HAS_DRTIO"] = None
        self.config["HAS_DRTIO_ROUTING"] = None
        self.add_csr_group("drtio", drtio_csr_group)
        self.add_csr_group("drtioaux", drtioaux_csr_group)
        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)

        self.config["RTIO_FREQUENCY"] = str(
            self.drtio_transceiver.rtio_clk_freq / 1e6)
        self.submodules.si5324_rst_n = gpio.GPIOOut(
            platform.request("si5324").rst_n)
        self.csr_devices.append("si5324_rst_n")
        i2c = self.platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.csr_devices.append("i2c")
        self.config["I2C_BUS_COUNT"] = 1
        self.config["HAS_SI5324"] = None
        self.config["SI5324_AS_SYNTHESIZER"] = None

        self.comb += [
            platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
            platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
        ]

        rtio_clk_period = 1e9 / self.drtio_transceiver.rtio_clk_freq
        # Constrain TX & RX timing for the first transceiver channel
        # (First channel acts as master for phase alignment for all channels' TX)
        gtx0 = self.drtio_transceiver.gtxs[0]
        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
        platform.add_false_path_constraints(self.crg.cd_sys.clk, gtx0.txoutclk,
                                            gtx0.rxoutclk)
        # Constrain RX timing for the each transceiver channel
        # (Each channel performs single-lane phase alignment for RX)
        for gtx in self.drtio_transceiver.gtxs[1:]:
            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
            platform.add_false_path_constraints(self.crg.cd_sys.clk,
                                                gtx0.txoutclk, gtx.rxoutclk)

        rtio_channels = []
        for i in range(8):
            phy = ttl_simple.Output(platform.request("user_led", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        for sma in "user_sma_gpio_p", "user_sma_gpio_n":
            phy = ttl_simple.InOut(platform.request(sma))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))

        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
        self.csr_devices.append("rtio_moninj")

        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
        self.csr_devices.append("rtio_core")

        self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
        self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
            self.get_native_sdram_if()))
        self.register_kernel_cpu_csrdevice("rtio")
        self.register_kernel_cpu_csrdevice("rtio_dma")
        self.submodules.cri_con = rtio.CRIInterconnectShared(
            [self.rtio.cri, self.rtio_dma.cri],
            [self.rtio_core.cri] + drtio_cri,
            enable_routing=True)
        self.register_kernel_cpu_csrdevice("cri_con")
        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
        self.csr_devices.append("routing_table")
    def __init__(self, **kwargs):
        MiniSoC.__init__(self,
                         cpu_type="or1k",
                         sdram_controller_type="minicon",
                         l2_size=128 * 1024,
                         with_timer=False,
                         ident="DRTIO_DEMO",
                         **kwargs)
        AMPSoC.__init__(self)

        platform = self.platform
        platform.add_extension(ttl_extension)

        rtio_channels = []
        phy = ttl_simple.Output(platform.request("user_sma_gpio_p"))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy))
        phy = ttl_simple.Output(platform.request("user_sma_gpio_n"))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy))
        for i in range(8):
            phy = ttl_simple.Output(platform.request("user_led"))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        for i in range(22):
            phy = ttl_simple.Output(platform.request("ttl"))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))
        self.comb += platform.request("sfp_tx_disable_n").eq(1)
        self.submodules.remote_ttl_channels = RemoteTTLChannels(
            clock_pads=platform.request("sgmii_clock"),
            tx_pads=platform.request("sfp_tx"),
            sys_clk_freq=125000000)
        rtio_channels += self.remote_ttl_channels.rtio_channels
        self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
        rtio_channels.append(rtio.LogChannel())

        sma = platform.request("user_sma_clock_p")
        self.comb += sma.eq(ClockSignal("tx"))

        self.submodules.rtio = rtio.RTIO(rtio_channels)
        self.register_kernel_cpu_csrdevice("rtio")
        self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)

        self.specials += [
            Keep(self.rtio.cd_rsys.clk),
            Keep(self.remote_ttl_channels.cd_rtio.clk),
            Keep(self.ethphy.crg.cd_eth_rx.clk),
            Keep(self.ethphy.crg.cd_eth_tx.clk),
        ]

        platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)
        platform.add_period_constraint(self.remote_ttl_channels.cd_rtio.clk,
                                       16.)
        platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
        platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
        platform.add_false_path_constraints(
            self.rtio.cd_rsys.clk, self.remote_ttl_channels.cd_rtio.clk,
            self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)

        self.submodules.rtio_analyzer = rtio.Analyzer(
            self.rtio, self.get_native_sdram_if())
Esempio n. 14
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    def __init__(self, cpu_type="or1k", **kwargs):
        MiniSoC.__init__(self,
                         cpu_type=cpu_type,
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         ident=artiq_version,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        self.platform.toolchain.bitstream_commands.extend([
            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
        ])

        platform = self.platform
        platform.add_extension(ad9154_fmc_ebz)

        self.submodules.leds = gpio.GPIOOut(Cat(
            platform.request("user_led", 0),
            platform.request("user_led", 1)))
        self.csr_devices.append("leds")

        i2c = platform.request("i2c")
        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
        self.csr_devices.append("i2c")
        self.config["I2C_BUS_COUNT"] = 1

        ad9154_spi = platform.request("ad9154_spi")
        self.comb += ad9154_spi.en.eq(1)
        self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
        self.csr_devices.append("converter_spi")
        self.config["CONVERTER_SPI_DAC_CS"] = 0
        self.config["CONVERTER_SPI_CLK_CS"] = 1
        self.config["HAS_AD9516"] = None

        self.submodules.ad9154 = AD9154(platform)
        self.csr_devices.append("ad9154")

        rtio_channels = []

        phy = ttl_serdes_7series.InOut_8X(
            platform.request("user_sma_gpio_n"))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))

        phy = ttl_simple.Output(platform.request("user_led", 2))
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy))

        sysref_pads = platform.request("ad9154_sysref")
        phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
        self.submodules += phy
        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
                                                   ofifo_depth=2))

        self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
        rtio_channels.extend(rtio.Channel.from_phy(phy)
                             for sawg in self.ad9154.sawgs
                             for phy in sawg.phys)

        self.config["HAS_RTIO_LOG"] = None
        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
        rtio_channels.append(rtio.LogChannel())

        self.submodules.rtio_crg = _PhaserCRG(
            platform, self.ad9154.jesd.cd_jesd.clk)
        self.csr_devices.append("rtio_crg")
        self.submodules.rtio_core = rtio.Core(rtio_channels)
        self.csr_devices.append("rtio_core")
        self.submodules.rtio = rtio.KernelInitiator()
        self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
            rtio.DMA(self.get_native_sdram_if()))
        self.register_kernel_cpu_csrdevice("rtio")
        self.register_kernel_cpu_csrdevice("rtio_dma")
        self.submodules.cri_con = rtio.CRIInterconnectShared(
            [self.rtio.cri, self.rtio_dma.cri],
            [self.rtio_core.cri])
        self.register_kernel_cpu_csrdevice("cri_con")
        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
        self.csr_devices.append("rtio_moninj")
        self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
                                                      self.get_native_sdram_if())
        self.csr_devices.append("rtio_analyzer")

        platform.add_false_path_constraints(
            self.crg.cd_sys.clk, self.rtio_crg.cd_rtio.clk)
        platform.add_false_path_constraints(
            self.crg.cd_sys.clk, self.ad9154.jesd.cd_jesd.clk)
        for phy in self.ad9154.jesd.phys:
            platform.add_false_path_constraints(
                self.crg.cd_sys.clk, phy.transmitter.cd_tx.clk)