Esempio n. 1
0
    def __call__(self, func, *args, **kwargs):

        vals = {}
        vals['topname'] = func.func_name
        vals['unitname'] = func.func_name.lower()
        vals['version'] = _version

        hdlsim = self.simulator
        if not hdlsim:
            raise ValueError("No simulator specified")
        if not hdlsim in _simulators:
            raise ValueError("Simulator %s is not registered" % hdlsim)
        hdl = _hdlMap[hdlsim]
        analyze = _analyzeCommands[hdlsim] % vals
        elaborate = _elaborateCommands[hdlsim]
        if elaborate is not None:
            elaborate = elaborate % vals
        simulate = _simulateCommands[hdlsim] % vals
        skiplines = _skiplinesMap[hdlsim]
        skipchars = _skipcharsMap[hdlsim]
        ignore = _ignoreMap[hdlsim]

        if hdl == "VHDL":
            inst = toVHDL(func, *args, **kwargs)
        else:
            inst = toVerilog(func, *args, **kwargs)

        if hdl == "VHDL":
            if not os.path.exists("work"):
                os.mkdir("work")
        if hdlsim in ('vlog', 'vcom'):
            if not os.path.exists("work_vsim"):
                try:
                    subprocess.call("vlib work_vlog", shell=True)
                    subprocess.call("vlib work_vcom", shell=True)
                    subprocess.call("vmap work_vlog work_vlog", shell=True)
                    subprocess.call("vmap work_vcom work_vcom", shell=True)
                except:
                    pass

        ret = subprocess.call(analyze, shell=True)
        if ret != 0:
            print >> sys.stderr, "Analysis failed"
            return ret

        if self._analyzeOnly:
            print >> sys.stderr, "Analysis succeeded"
            return 0

        f = tempfile.TemporaryFile()
        sys.stdout = f
        sim = Simulation(inst)
        sim.run()
        sys.stdout = sys.__stdout__
        f.flush()
        f.seek(0)

        flines = f.readlines()
        f.close()
        if not flines:
            print >> sys.stderr, "No MyHDL simulation output - nothing to verify"
            return 1

        if elaborate is not None:
            ret = subprocess.call(elaborate, shell=True)
            if ret != 0:
                print >> sys.stderr, "Elaboration failed"
                return ret

        g = tempfile.TemporaryFile()
        ret = subprocess.call(simulate, stdout=g, shell=True)
        #    if ret != 0:
        #        print "Simulation run failed"
        #        return
        g.flush()
        g.seek(0)

        glines = g.readlines()[skiplines:]
        if ignore:
            for p in ignore:
                glines = [line for line in glines if not line.startswith(p)]
        # limit diff window to the size of the MyHDL output
        # this is a hack to remove an eventual simulator postamble
        if len(glines) > len(flines):
            glines = glines[:len(flines)]
        glines = [line[skipchars:] for line in glines]
        flinesNorm = [line.lower() for line in flines]
        glinesNorm = [line.lower() for line in glines]
        g = difflib.unified_diff(flinesNorm,
                                 glinesNorm,
                                 fromfile=hdlsim,
                                 tofile=hdl)

        MyHDLLog = "MyHDL.log"
        HDLLog = hdlsim + ".log"
        try:
            os.remove(MyHDLLog)
            os.remove(HDLLog)
        except:
            pass

        s = "".join(g)
        f = open(MyHDLLog, 'w')
        g = open(HDLLog, 'w')
        d = open('diff.log', 'w')
        f.writelines(flines)
        g.writelines(glines)
        d.write(s)
        f.close()
        g.close()
        d.close()

        if not s:
            print >> sys.stderr, "Conversion verification succeeded"
        else:
            print >> sys.stderr, "Conversion verification failed"
            # print >> sys.stderr, s ,
            return 1

        return 0
Esempio n. 2
0
    def __call__(self, func, *args, **kwargs):

        vals = {}
        vals["topname"] = func.func_name
        vals["unitname"] = func.func_name.lower()
        vals["version"] = _version

        hdlsim = self.simulator
        if not hdlsim:
            raise ValueError("No simulator specified")
        if not hdlsim in _simulators:
            raise ValueError("Simulator %s is not registered" % hdlsim)
        hdl = _hdlMap[hdlsim]
        analyze = _analyzeCommands[hdlsim] % vals
        elaborate = _elaborateCommands[hdlsim]
        if elaborate is not None:
            elaborate = elaborate % vals
        simulate = _simulateCommands[hdlsim] % vals
        skiplines = _skiplinesMap[hdlsim]
        skipchars = _skipcharsMap[hdlsim]
        ignore = _ignoreMap[hdlsim]

        if hdl == "VHDL":
            inst = toVHDL(func, *args, **kwargs)
        else:
            inst = toVerilog(func, *args, **kwargs)

        if hdl == "VHDL":
            if not os.path.exists("work"):
                os.mkdir("work")
        if hdlsim in ("vlog", "vcom"):
            if not os.path.exists("work_vsim"):
                try:
                    subprocess.call("vlib work_vlog", shell=True)
                    subprocess.call("vlib work_vcom", shell=True)
                    subprocess.call("vmap work_vlog work_vlog", shell=True)
                    subprocess.call("vmap work_vcom work_vcom", shell=True)
                except:
                    pass

        ret = subprocess.call(analyze, shell=True)
        if ret != 0:
            print >>sys.stderr, "Analysis failed"
            return ret

        if self._analyzeOnly:
            print >>sys.stderr, "Analysis succeeded"
            return 0

        f = tempfile.TemporaryFile()
        sys.stdout = f
        sim = Simulation(inst)
        sim.run()
        sys.stdout = sys.__stdout__
        f.flush()
        f.seek(0)

        flines = f.readlines()
        f.close()
        if not flines:
            print >>sys.stderr, "No MyHDL simulation output - nothing to verify"
            return 1

        if elaborate is not None:
            ret = subprocess.call(elaborate, shell=True)
            if ret != 0:
                print >>sys.stderr, "Elaboration failed"
                return ret

        g = tempfile.TemporaryFile()
        ret = subprocess.call(simulate, stdout=g, shell=True)
        #    if ret != 0:
        #        print "Simulation run failed"
        #        return
        g.flush()
        g.seek(0)

        glines = g.readlines()[skiplines:]
        if ignore:
            for p in ignore:
                glines = [line for line in glines if not line.startswith(p)]
        # limit diff window to the size of the MyHDL output
        # this is a hack to remove an eventual simulator postamble
        if len(glines) > len(flines):
            glines = glines[: len(flines)]
        glines = [line[skipchars:] for line in glines]
        flinesNorm = [line.lower() for line in flines]
        glinesNorm = [line.lower() for line in glines]
        g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile=hdlsim, tofile=hdl)

        MyHDLLog = "MyHDL.log"
        HDLLog = hdlsim + ".log"
        try:
            os.remove(MyHDLLog)
            os.remove(HDLLog)
        except:
            pass

        s = "".join(g)
        f = open(MyHDLLog, "w")
        g = open(HDLLog, "w")
        d = open("diff.log", "w")
        f.writelines(flines)
        g.writelines(glines)
        d.write(s)
        f.close()
        g.close()
        d.close()

        if not s:
            print >>sys.stderr, "Conversion verification succeeded"
        else:
            print >>sys.stderr, "Conversion verification failed"
            # print >> sys.stderr, s ,
            return 1

        return 0
Esempio n. 3
0
    def __call__(self, func, *args, **kwargs):

        if not self.simulator:
            raise ValueError("No simulator specified")
        if  self.simulator not in _simulators:
            raise ValueError("Simulator %s is not registered" % self.simulator)
        hdlsim = _simulators[self.simulator]
        hdl = hdlsim.hdl
        if hdl == 'Verilog' and toVerilog.name is not None:
            name = toVerilog.name
        elif hdl == 'VHDL' and toVHDL.name is not None:
            name = toVHDL.name
        else:
            name = func.__name__

        vals = {}
        vals['topname'] = name
        vals['unitname'] = name.lower()
        vals['version'] = _version

        analyze = hdlsim.analyze % vals
        elaborate = hdlsim.elaborate
        if elaborate is not None:
            elaborate = elaborate % vals
        simulate = hdlsim.simulate % vals
        skiplines = hdlsim.skiplines
        skipchars = hdlsim.skipchars
        ignore = hdlsim.ignore

        if hdl == "VHDL":
            inst = toVHDL(func, *args, **kwargs)
        else:
            inst = toVerilog(func, *args, **kwargs)

        if hdl == "VHDL":
            if not os.path.exists("work"):
                os.mkdir("work")
        if hdlsim.name in ('vlog', 'vcom'):
            if not os.path.exists("work_vsim"):
                try:
                    subprocess.call("vlib work_vlog", shell=True)
                    subprocess.call("vlib work_vcom", shell=True)
                    subprocess.call("vmap work_vlog work_vlog", shell=True)
                    subprocess.call("vmap work_vcom work_vcom", shell=True)
                except:
                    pass

        #print(analyze)
        ret = subprocess.call(analyze, shell=True)
        if ret != 0:
            print("Analysis failed", file=sys.stderr)
            return ret

        if self._analyzeOnly:
            print("Analysis succeeded", file=sys.stderr)
            return 0

        f = tempfile.TemporaryFile(mode='w+t')
        sys.stdout = f
        sim = Simulation(inst)
        sim.run()
        sys.stdout = sys.__stdout__
        f.flush()
        f.seek(0)

        flines = f.readlines()
        f.close()
        if not flines:
            print("No MyHDL simulation output - nothing to verify", file=sys.stderr)
            return 1


        if elaborate is not None:
            #print(elaborate)
            ret = subprocess.call(elaborate, shell=True)
            if ret != 0:
                print("Elaboration failed", file=sys.stderr)
                return ret

        g = tempfile.TemporaryFile(mode='w+t')
        #print(simulate)
        ret = subprocess.call(simulate, stdout=g, shell=True)
    #    if ret != 0:
    #        print "Simulation run failed"
    #        return
        g.flush()
        g.seek(0)

        glines = g.readlines()[skiplines:]
        if ignore:
            for p in ignore:
                glines = [line for line in glines if not line.startswith(p)]
        # limit diff window to the size of the MyHDL output
        # this is a hack to remove an eventual simulator postamble
        if len(glines) > len(flines):
            glines = glines[:len(flines)]
        glines = [line[skipchars:] for line in glines]
        flinesNorm = [line.lower() for line in flines]
        glinesNorm = [line.lower() for line in glines]
        g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile='MyHDL', tofile=hdlsim.name)

        MyHDLLog = "MyHDL.log"
        HDLLog = hdlsim.name + ".log"
        try:
            os.remove(MyHDLLog)
            os.remove(HDLLog)
        except:
            pass

        s = "".join(g)
        f = open(MyHDLLog, 'w')
        g = open(HDLLog, 'w')
        d = open('diff.log', 'w')
        f.writelines(flines)
        g.writelines(glines)
        d.write(s)
        f.close()
        g.close()
        d.close()

        if not s:
            print("Conversion verification succeeded", file=sys.stderr)
        else:
            print("Conversion verification failed", file=sys.stderr)
            # print >> sys.stderr, s ,
            return 1

        return 0
Esempio n. 4
0
    def __call__(self, func, *args, **kwargs):

        if not self.simulator:
            raise ValueError("No simulator specified")
        if self.simulator not in _simulators:
            raise ValueError("Simulator %s is not registered" % self.simulator)
        hdlsim = _simulators[self.simulator]
        hdl = hdlsim.hdl
        if hdl == 'Verilog' and toVerilog.name is not None:
            name = toVerilog.name
        elif hdl == 'SystemVerilog' and toSystemVerilog.name is not None:
            name = toSystemVerilog.name
        elif hdl == 'VHDL' and toVHDL.name is not None:
            name = toVHDL.name
        elif isinstance(func, _Block):
            name = func.func.__name__
        else:
            warnings.warn(
                "\n    analyze()/verify(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2)
            try:
                name = func.__name__
            except:
                raise TypeError(str(type(func)))

        vals = {}
        vals['topname'] = name
        vals['unitname'] = name.lower()
        vals['version'] = _version

        analyze = hdlsim.analyze % vals
        elaborate = hdlsim.elaborate
        if elaborate is not None:
            elaborate = elaborate % vals
        simulate = hdlsim.simulate % vals
        skiplines = hdlsim.skiplines
        skipchars = hdlsim.skipchars
        ignore = hdlsim.ignore

        if isinstance(func, _Block):
            if hdl == "VHDL":
                inst = func.convert(hdl='VHDL')
            elif hdl == "SystemVerilog":
                inst = func.convert(hdl='SystemVerilog')
            else:
                inst = func.convert(hdl='Verilog')
        else:
            if hdl == "VHDL":
                inst = toVHDL(func, *args, **kwargs)
            elif hdl == "SystemVerilog":
                inst = toSystemVerilog(func, *args, **kwargs)
            else:
                inst = toVerilog(func, *args, **kwargs)

        if hdl == "VHDL":
            if not os.path.exists("work"):
                os.mkdir("work")
        if hdlsim.name in ('vlog', 'vcom'):
            if not os.path.exists("work_vsim"):
                try:
                    subprocess.call("vlib work_vlog", shell=True)
                    subprocess.call("vlib work_vcom", shell=True)
                    subprocess.call("vmap work_vlog work_vlog", shell=True)
                    subprocess.call("vmap work_vcom work_vcom", shell=True)
                except:
                    pass

        # print(analyze)
        ret = subprocess.call(analyze, shell=True)
        if ret != 0:
            print("Analysis failed", file=sys.stderr)
            return ret

        if self._analyzeOnly:
            print("Analysis succeeded", file=sys.stderr)
            return 0

        f = tempfile.TemporaryFile(mode='w+t')
        sys.stdout = f
        sim = Simulation(inst)
        sim.run()
        sys.stdout = sys.__stdout__
        f.flush()
        f.seek(0)

        flines = f.readlines()
        f.close()
        if not flines:
            print("No MyHDL simulation output - nothing to verify", file=sys.stderr)
            return 1

        if elaborate is not None:
            # print(elaborate)
            ret = subprocess.call(elaborate, shell=True)
            if ret != 0:
                print("Elaboration failed", file=sys.stderr)
                return ret

        g = tempfile.TemporaryFile(mode='w+t')
        # print(simulate)
        ret = subprocess.call(simulate, stdout=g, shell=True)
    #    if ret != 0:
    #        print "Simulation run failed"
    #        return
        g.flush()
        g.seek(0)

        glines = g.readlines()[skiplines:]
        if ignore:
            for p in ignore:
                glines = [line for line in glines if not line.startswith(p)]
        # limit diff window to the size of the MyHDL output
        # this is a hack to remove an eventual simulator postamble
        if len(glines) > len(flines):
            glines = glines[:len(flines)]
        glines = [line[skipchars:] for line in glines]
        flinesNorm = [line.lower() for line in flines]
        glinesNorm = [line.lower() for line in glines]
        g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile='MyHDL', tofile=hdlsim.name)

        MyHDLLog = "MyHDL.log"
        HDLLog = hdlsim.name + ".log"
        try:
            os.remove(MyHDLLog)
            os.remove(HDLLog)
        except:
            pass

        s = "".join(g)
        f = open(MyHDLLog, 'w')
        g = open(HDLLog, 'w')
        d = open('diff.log', 'w')
        f.writelines(flines)
        g.writelines(glines)
        d.write(s)
        f.close()
        g.close()
        d.close()

        if not s:
            print("Conversion verification succeeded", file=sys.stderr)
        else:
            print("Conversion verification failed", file=sys.stderr)
            # print >> sys.stderr, s ,
            return 1

        return 0
Esempio n. 5
0
    def __call__(self, func, *args, **kwargs):

        vals = {}
        vals['topname'] = func.func_name
        vals['unitname'] = func.func_name.lower()
        vals['version'] = _version

        hdlsim = self.simulator
        if not hdlsim:
            raise ValueError("No simulator specified")
        if  not hdlsim in _simulators:
            raise ValueError("Simulator %s is not registered" % hdlsim)
        hdl  = _hdlMap[hdlsim]
        analyze = _analyzeCommands[hdlsim] % vals
        elaborate = _elaborateCommands[hdlsim]
        if elaborate is not None:
            elaborate = elaborate % vals
        simulate = _simulateCommands[hdlsim] % vals
        offset = _offsets[hdlsim]

        if hdl == "VHDL":
            inst = toVHDL(func, *args, **kwargs)
        else:
            inst = toVerilog(func, *args, **kwargs)

        if hdl == "VHDL":
            if not os.path.exists("work"):
                os.mkdir("work")
        ret = subprocess.call(analyze, shell=True)
        if ret != 0:
            print >> sys.stderr, "Analysis failed"
            return ret

        if self._analyzeOnly:
            print >> sys.stderr, "Analysis succeeded"
            return 0

        f = tempfile.TemporaryFile()
        sys.stdout = f
        sim = Simulation(inst)
        sim.run()
        sys.stdout = sys.__stdout__
        f.flush()
        f.seek(0)

        flines = f.readlines()
        f.close()
        if not flines:
            print >> sys.stderr, "No MyHDL simulation output - nothing to verify"
            return 1


        if elaborate is not None:
            ret = subprocess.call(elaborate, shell=True)
            if ret != 0:
                print >> sys.stderr, "Elaboration failed"
                return ret
            
        g = tempfile.TemporaryFile()
        ret = subprocess.call(simulate, stdout=g, shell=True)
    #    if ret != 0:
    #        print "Simulation run failed"
    #        return
        g.flush()
        g.seek(0)

        glines = g.readlines()[offset:]
        flinesNorm = [line.lower() for line in flines]
        glinesNorm = [line.lower() for line in glines]
        g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile=hdlsim, tofile=hdl)

        MyHDLLog = "MyHDL.log"
        HDLLog = hdlsim + ".log"
        try:
            os.remove(MyHDLLog)
            os.remove(HDLLog)
        except:
            pass


        s = "".join(g)
        f = open(MyHDLLog, 'w')
        g = open(HDLLog, 'w')
        f.writelines(flines)
        g.writelines(glines)


        if not s:
            print >> sys.stderr, "Conversion verification succeeded"
        else:
            print >> sys.stderr, "Conversion verification failed"
            # print >> sys.stderr, s ,
            return 1

        return 0