def ts_rd_commanded(tsm):
fpga_tsms = []
sessions = []
tests_pins = [["RIO_Pins"]]
for test_pin_group in tests_pins:
data = ni_fpga.pins_to_sessions(tsm, test_pin_group)
fpga_tsms.append(data)
sessions += data.SSC
print(fpga_tsms[0].read_commanded_line_states())
def fpga_tsm_s(tsm, tests_pins):
"""Returns LabVIEW Cluster equivalent data"""
fpga_tsms = []
sessions = []
for test_pin_group in tests_pins:
data = ni_fpga.pins_to_sessions(tsm, test_pin_group)
fpga_tsms.append(data)
sessions += data.SSC
print(len(sessions))
yield tsm, fpga_tsms
def ts_wr_and_rd(tsm):
fpga_tsms = []
sessions = []
tests_pins = [["RIO_Pins"]]
for test_pin_group in tests_pins:
data = ni_fpga.pins_to_sessions(tsm, test_pin_group)
fpga_tsms.append(data)
sessions += data.SSC
fpga_session7821 = fpga_tsms[0].SSC[1]
fpga_session7820 = fpga_tsms[0].SSC[0]
print("Start", fpga_session7821.read_all_lines())
for i in range(8):
fpga_session7820.write_single_dio_line(ni_fpga.Connectors.Connector0,
ni_fpga.DIOLines(i),
ni_fpga.StaticStates.Zero)
print("Mid", fpga_session7821.read_all_lines())
fpga_session7820.write_single_dio_line(ni_fpga.Connectors.Connector0,
ni_fpga.DIOLines.DIO7,
ni_fpga.StaticStates.One)
print("End", fpga_session7821.read_all_lines())
# assert(fpga_session7821.read_all_lines().Connector0 == 128)
fpga_session7820.write_single_dio_line(ni_fpga.Connectors.Connector0,
ni_fpga.DIOLines.DIO7,
ni_fpga.StaticStates.Zero)
# assert (fpga_session7821.read_all_lines().Connector0 == 0)
wr1 = ni_fpga.DIOLineLocationAndStaticState(ni_fpga.DIOLines(7),
ni_fpga.Connectors(0),
ni_fpga.StaticStates(0))
wr2 = ni_fpga.DIOLineLocationAndStaticState(ni_fpga.DIOLines(6),
ni_fpga.Connectors(0),
ni_fpga.StaticStates(1))
fpga_session7820.write_multiple_dio_lines([wr2, wr1])
assert (fpga_session7821.read_single_dio_line(
ni_fpga.Connectors.Connector0, ni_fpga.DIOLines.DIO6) == "1")
assert (fpga_session7821.read_single_dio_line(
ni_fpga.Connectors.Connector0, ni_fpga.DIOLines.DIO7) == "0")
assert fpga_session7821.read_single_connector(ni_fpga.Connectors(0)) == 64
data = fpga_session7821.read_multiple_lines([
ni_fpga.LineLocation(ni_fpga.DIOLines(7), ni_fpga.Connectors(0)),
ni_fpga.LineLocation(ni_fpga.DIOLines(6), ni_fpga.Connectors(0)),
])
assert data[0].state == "0"
assert data[1].state == "1"
data = fpga_session7821.read_multiple_dio_commanded_states([
ni_fpga.LineLocation(ni_fpga.DIOLines(7), ni_fpga.Connectors(0)),
ni_fpga.LineLocation(ni_fpga.DIOLines(6), ni_fpga.Connectors(0)),
])
assert data[0].channel == ni_fpga.DIOLines.DIO7
assert data[1].channel == ni_fpga.DIOLines.DIO6
assert data[0].connector == data[0].connector
def ts_rd_wr_static(tsm):
fpga_tsms = []
sessions = []
tests_pins = [["RIO_Pins"]]
for test_pin_group in tests_pins:
data = ni_fpga.pins_to_sessions(tsm, test_pin_group)
fpga_tsms.append(data)
sessions += data.SSC
fpga_tsms[0].write_static([ni_fpga.StaticStates.Zero] * 128)
list_s = fpga_tsms[0].read_static()
for data in list_s[0][0]:
assert data.state == "0"
fpga_tsms[0].write_static([ni_fpga.StaticStates.One] * 128)
list_s = fpga_tsms[0].read_static()
for data in list_s[0][0]:
print(data.state)
fpga_tsms[0].write_static([ni_fpga.StaticStates.Zero] * 128)
list_s = fpga_tsms[0].read_static()
for data in list_s[0][0]:
assert data.state == "0"
def ts_wr(tsm):
fpga_tsms = []
sessions = []
tests_pins = [["RIO_Pins"]]
for test_pin_group in tests_pins:
data = ni_fpga.pins_to_sessions(tsm, test_pin_group)
fpga_tsms.append(data)
sessions += data.SSC
fpga_session7821 = fpga_tsms[0].SSC[1]
fpga_session7820 = fpga_tsms[0].SSC[0]
for i in range(4):
con_enable = fpga_session7820.Session.registers[
"Connector%d Output Enable" % i]
con_data = fpga_session7820.Session.registers["Connector%d Output Data"
% i]
con_enable.write(0)
con_data.write(0)
print("READ_CON", con_enable.read(), con_data.read())
print(
"READ",
fpga_session7821.Session.registers["Connector%d Read Data" %
i].read())