def test_regime(self):
# Signature: name(self, name=None)
# Find a regime in the component by name
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
c = ComponentClass(name='cl',
regimes=[
Regime('dX/dt=0',
name='r1',
transitions=On('X>X1',
do=['X=X0'],
to='r2')),
Regime('dX/dt=0',
name='r2',
transitions=On('X>X1',
do=['X=X0'],
to='r3')),
Regime('dX/dt=0',
name='r3',
transitions=On('X>X1',
do=['X=X0'],
to='r4')),
Regime('dX/dt=0',
name='r4',
transitions=On('X>X1',
do=['X=X0'],
to='r1')),
])
self.assertEqual(c.query.regime(name='r1').name, 'r1')
self.assertEqual(c.query.regime(name='r2').name, 'r2')
self.assertEqual(c.query.regime(name='r3').name, 'r3')
self.assertEqual(c.query.regime(name='r4').name, 'r4')
def test_name(self):
self.assertRaises(NineMLRuntimeError, Regime, name='&Hello')
self.assertRaises(NineMLRuntimeError, Regime, name='2Hello')
self.assertEqual(Regime(name=' Hello ').name, 'Hello')
self.assertEqual(Regime(name=' Hello2 ').name, 'Hello2')
def test_get_next_name(self):
# Signature: name(cls)
# Return the next distinct autogenerated name
n1 = Regime.get_next_name()
n2 = Regime.get_next_name()
n3 = Regime.get_next_name()
self.assertNotEqual(n1, n2)
self.assertNotEqual(n2, n3)
def functest(self):
cc = ComponentClass(
name='PulsingCurrentClamp',
parameters=['i', 'cycle_length'],
analog_ports=[SendPort('I')],
regimes=[
Regime(
name='off',
transitions=On('t > tchange + cycle_length',
do=['tchange = t', 'I = 0'],
to='on'),
),
Regime(
name='on',
transitions=On('t > tchange + cycle_length',
do=['tchange = t', 'I = i'],
to='off'),
),
])
nrn = ComponentClass(
name='LeakyNeuron',
parameters=['Cm', 'gL', 'E'],
regimes=[
Regime('dV/dt = (iInj + (E-V)*gL )/Cm'),
],
analog_ports=[SendPort('V'),
ReducePort('iInj', reduce_op='+')],
)
combined_comp = ComponentClass(name='Comp1',
subnodes={
'nrn': nrn,
'cc1': cc
},
portconnections=[('cc1.I', 'nrn.iInj')])
records = [
RecordValue(what='cc1_I', tag='Current', label='Current Clamp 1'),
RecordValue(what='nrn_V', tag='Voltage', label='Neuron Voltage'),
RecordValue(what='cc1_tchange', tag='Tchange', label='tChange'),
RecordValue(what='regime', tag='Regime', label='Regime'),
]
parameters = {
'cc1_i': 13.8,
'cc1_cycle_length': 20,
'nrn_gL': 2,
'nrn_E': -70
}
results = std_pynn_simulation(test_component=combined_comp,
parameters=parameters,
initial_values={},
synapse_components=[],
records=records,
plot=True)
def test_event_ports(self):
# Signature: name
# No Docstring
# Check inference of output event ports:
c = ComponentClass(
name='Comp1',
regimes=Regime(transitions=[
On('V > a', do=OutputEvent('ev_port1')),
On('V > b', do=OutputEvent('ev_port1')),
On('V < c', do=OutputEvent('ev_port2')),
]),
)
self.assertEquals(len(list(c.event_ports)), 2)
# Check inference of output event ports:
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('V > a',
do=OutputEvent('ev_port1'),
to='r2'),
On('V < b',
do=OutputEvent('ev_port2')),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2'),
to='r1'),
On('V < b',
do=OutputEvent('ev_port3')),
])
])
self.assertEquals(len(list(c.event_ports)), 3)
# Check inference of output event ports:
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2',
do=OutputEvent('ev_port2'),
to='r2'),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2')),
On('spikeinput3',
do=OutputEvent('ev_port3'),
to='r1'),
])
])
self.assertEquals(len(list(c.event_ports)), 5)
def test_get_next_name(self):
# Signature: name(cls)
# Return the next distinct autogenerated name
n1 = Regime.get_next_name()
n2 = Regime.get_next_name()
n3 = Regime.get_next_name()
self.assertNotEqual(n1, n2)
self.assertNotEqual(n2, n3)
def test_transitions(self):
c = ComponentClass(
name='cl',
dynamicsblock=DynamicsBlock(regimes=[
Regime('dX1/dt=0',
name='r1',
transitions=[
On('X>X1', do=['X=X0'], to='r2'),
On('X>X2', do=['X=X0'], to='r3'),
]),
Regime(
'dX1/dt=0',
name='r2',
transitions=On('X>X1', do=['X=X0'], to='r3'),
),
Regime('dX2/dt=0',
name='r3',
transitions=[
On('X>X1', do=['X=X0'], to='r4'),
On('X>X2', do=['X=X0'], to=None)
]),
Regime('dX2/dt=0',
name='r4',
transitions=On('X>X1', do=['X=X0'], to=None)),
]))
self.assertEquals(len(list(c.transitions)), 6)
r_map = c.regimes_map
r1 = r_map['r1']
r2 = r_map['r2']
r3 = r_map['r3']
r4 = r_map['r4']
self.assertEquals(len(list(r1.transitions)), 2)
self.assertEquals(len(list(r2.transitions)), 1)
self.assertEquals(len(list(r3.transitions)), 2)
self.assertEquals(len(list(r4.transitions)), 1)
target_regimes = lambda r: set(
[tr.target_regime for tr in r.transitions])
self.assertEquals(target_regimes(r1), set([r2, r3]))
self.assertEquals(target_regimes(r2), set([r3]))
self.assertEquals(target_regimes(r3), set([r3, r4]))
self.assertEquals(target_regimes(r4), set([r4]))
def get_component():
off_regime = Regime(name="off_regime",
time_derivatives=[
"dRon/dt = -Ron/Rtau",
"dRoff/dt = -Beta*Roff",
],
transitions=On('spikeoutput',
do=[
"t_off = t+Cdur",
"r0 = r0*exp(-Beta*(t - t0))",
"t0 = t", "Ron = Ron +r0",
"Roff = Roff - r0"
],
to="on_regime"))
on_regime = Regime(
name="on_regime",
time_derivatives=[
"dRon/dt = (weight*Rinf - Ron)/Rtau",
"dRoff/dt = -Beta*Roff",
],
transitions=[
On('spikeoutput', do="t_off = t+Cdur"
), # Extend duration if input spike arrives while on
On(
"t_off>t", # What to do when its time to turn off
do=[
"r0 = weight*Rinf + (r0 - weight*Rinf)*exp(-(t - t0)/Rtau)",
"t0 = t", "Ron = Ron - r0", "Roff = Roff - r0"
],
to='off_regime')
])
analog_ports = [
RecvPort("weight"),
RecvPort("V"),
SendPort("Isyn"),
SendPort("gsyn")
]
c1 = ComponentClass(
"AMPA",
regimes=[off_regime, on_regime],
analog_ports=analog_ports,
aliases=["g := (on + off)", "Isyn := g*(E-V)", "gsyn := g"])
return c1
def test_parameters(self):
# Signature: name
# No Docstring
# No parameters; nothing to infer
c = ComponentClass(name='cl')
self.assertEqual(len(list(c.parameters)), 0)
# Mismatch between inferred and actual parameters
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='cl',
parameters=['a'])
# Single parameter inference from an alias block
c = ComponentClass(name='cl', aliases=['A:=a'])
self.assertEqual(len(list(c.parameters)), 1)
self.assertEqual(list(c.parameters)[0].name, 'a')
# More complex inference:
c = ComponentClass(name='cl', aliases=['A:=a+e', 'B:=a+pi+b'])
self.assertEqual(len(list(c.parameters)), 3)
self.assertEqual(sorted([p.name for p in c.parameters]),
['a', 'b', 'e'])
# From State Assignments and Differential Equations, and Conditionals
c = ComponentClass(
name='cl',
aliases=['A:=a+e', 'B:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On('V>Vt', do=['X = X + f', 'V=0'])))
self.assertEqual(len(list(c.parameters)), 7)
self.assertEqual(sorted([p.name for p in c.parameters]),
['Vt', 'a', 'b', 'c', 'd', 'e', 'f'])
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='cl',
aliases=['A:=a+e', 'B:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On(
'V>Vt', do=['X = X + f', 'V=0'])),
parameters=['a', 'b', 'c'])
def test_add_on_condition(self):
# Signature: name(self, on_condition)
# Add an OnCondition transition which leaves this regime
#
# If the on_condition object has not had its target regime name
# set in the constructor, or by calling its ``set_target_regime_name()``,
# then the target is assumed to be this regime, and will be set
# appropriately.
#
# The source regime for this transition will be set as this regime.
r = Regime(name="R1")
self.assertEquals(set(r.on_conditions), set())
self.assertRaises(NineMLRuntimeError, r.add_on_condition, OnEvent("sp1"))
r.add_on_condition(OnCondition("sp1>0"))
self.assertEquals(len(set(r.on_conditions)), 1)
self.assertEquals(len(set(r.on_events)), 0)
self.assertEquals(len(set(r.transitions)), 1)
def test_add_on_event(self):
# Signature: name(self, on_event)
# Add an OnEvent transition which leaves this regime
#
# If the on_event object has not had its target regime name
# set in the constructor, or by calling its ``set_target_regime_name()``,
# then the target is assumed to be this regime, and will be set
# appropriately.
#
# The source regime for this transition will be set as this regime.
# from nineml.abstraction_layer.component.dynamics import Regime
r = Regime(name='R1')
self.assertEquals(set(r.on_events), set())
self.assertRaises(NineMLRuntimeError, r.add_on_event, OnCondition('sp1>1'))
r.add_on_event(OnEvent('sp'))
self.assertEquals(len(set(r.on_events)), 1)
self.assertEquals(len(set(r.on_conditions)), 0)
self.assertEquals(len(set(r.transitions)), 1)
def test_state_variables(self):
# No parameters; nothing to infer
c = ComponentClass(name='cl')
self.assertEqual(len(list(c.state_variables)), 0)
# Mismatch between inferred and actual statevariables
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='cl',
state_variables=['a'])
# From State Assignments and Differential Equations, and Conditionals
c = ComponentClass(
name='cl',
aliases=['A:=a+e', 'B:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On('V>Vt', do=['X = X + f', 'V=0'])))
self.assertEqual(set(c.state_variables_map.keys()), set(['X', 'V']))
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='cl',
aliases=['A:=a+e', 'B:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On(
'V>Vt', do=['X = X + f', 'V=0'])),
state_variables=['X'])
# Shouldn't pick up 'e' as a parameter:
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='cl',
aliases=['A:=a+e', 'B:=a+pi+b'],
regimes=Regime('dX/dt = 6 + c + sin(d)',
'dV/dt = 1.0',
transitions=On(
'V>Vt', do=['X = X + f', 'V=0'])),
state_variables=['X', 'V', 'Vt'])
c = ComponentClass(
name='cl',
dynamicsblock=DynamicsBlock(regimes=[
Regime('dX1/dt=0',
name='r1',
transitions=On('X>X1', do=['X=X0'], to='r2')),
Regime('dX1/dt=0',
name='r2',
transitions=On('X>X1', do=['X=X0'], to='r3')),
Regime('dX2/dt=0',
name='r3',
transitions=On('X>X1', do=['X=X0'], to='r4')),
Regime('dX2/dt=0',
name='r4',
transitions=On('X>X1', do=['X=X0'], to='r1')),
]))
self.assertEqual(set(c.state_variables_map.keys()),
set(['X1', 'X2', 'X']))
def test_add_on_event(self):
# Signature: name(self, on_event)
# Add an OnEvent transition which leaves this regime
#
# If the on_event object has not had its target regime name
# set in the constructor, or by calling its ``set_target_regime_name()``,
# then the target is assumed to be this regime, and will be set
# appropriately.
#
# The source regime for this transition will be set as this regime.
# from nineml.abstraction_layer.component.dynamics import Regime
r = Regime(name='R1')
self.assertEquals(set(r.on_events), set())
self.assertRaises(NineMLRuntimeError, r.add_on_event,
OnCondition('sp1>1'))
r.add_on_event(OnEvent('sp'))
self.assertEquals(len(set(r.on_events)), 1)
self.assertEquals(len(set(r.on_conditions)), 0)
self.assertEquals(len(set(r.transitions)), 1)
def test_ports(self):
# Signature: name
# Return an iterator over all the port (Event & Analog) in the
# component
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2',
do=OutputEvent('ev_port2'),
to='r2'),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2')),
On('spikeinput3',
do=OutputEvent('ev_port3'),
to='r1'),
])
],
aliases=['A:=0', 'C:=0'],
analog_ports=[
AnalogSendPort('A'),
AnalogReceivePort('B'),
AnalogSendPort('C')
])
ports = list(c.query.ports)
port_names = [p.name for p in ports]
self.assertEquals(len(port_names), 8)
self.assertEquals(
set(port_names),
set([
'A', 'B', 'C', 'spikeinput1', 'spikeinput2', 'spikeinput3',
'ev_port2', 'ev_port3'
]))
def test1(self):
cc = ComponentClass(
name='SimpleCurrentClamp',
parameters=['i'],
analog_ports=[SendPort('I')],
aliases='I:=i',
)
nrn = ComponentClass(
name='LeakyNeuron',
parameters=['Cm', 'gL', 'E'],
regimes=[
Regime('dV/dt = (iInj + (E-V)*gL )/Cm'),
],
analog_ports=[SendPort('V'),
ReducePort('iInj', reduce_op='+')],
)
combined_comp = ComponentClass(name='Comp1',
subnodes={
'nrn': nrn,
'cc1': cc
},
portconnections=[('cc1.I', 'nrn.iInj')])
records = [
RecordValue(what='cc1_I', tag='Current', label='Current Clamp 1'),
RecordValue(what='nrn_V', tag='Voltage', label='Neuron Voltage'),
]
res = std_pynn_simulation(test_component=combined_comp,
parameters={
'cc1_i': 13.8,
'nrn_gL': 2,
'nrn_E': -70
},
initial_values={},
synapse_components=[],
records=records,
plot=False)
t, records = res
self.assertAlmostEqual(records['cc1_I'][t > 10].mean(), 13.8)
self.assertAlmostEqual(records['cc1_I'][t > 10].std(), 0.0)
self.assertAlmostEqual(records['nrn_V'][t > 10].mean(), -63.1)
self.assertAlmostEqual(records['nrn_V'][t > 10].std(), 0.0)
def test_accept_visitor(self):
# Signature: name(self, visitor, **kwargs)
# |VISITATION|
class TestVisitor(object):
def visit(self, obj, **kwargs):
return obj.accept_visitor(self, **kwargs)
def visit_regime(self, component, **kwargs):
return kwargs
c = Regime(name='R1')
v = TestVisitor()
self.assertEqual(v.visit(c, kwarg1='Hello', kwarg2='Hello2'), {
'kwarg1': 'Hello',
'kwarg2': 'Hello2'
})
def test_time_derivatives(self):
# Signature: name
# Returns the state-variable time-derivatives in this regime.
#
# .. note::
#
# This is not guarenteed to contain the time derivatives for all the
# state-variables specified in the component. If they are not defined,
# they are assumed to be zero in this regime.
r = Regime('dX1/dt=0', 'dX2/dt=0', name='r1')
self.assertEquals(
set([td.dependent_variable for td in r.time_derivatives]),
set(['X1', 'X2']))
# Defining a time derivative twice:
self.assertRaises(NineMLRuntimeError, Regime, 'dX/dt=1', 'dX/dt=2')
# Assigning to a value:
self.assertRaises(NineMLRuntimeError, Regime, 'X=1')
def func_test(self):
emitter = ComponentClass(
name='EventEmitter',
parameters=['cyclelength'],
regimes=[
Regime(transitions=On('t > tchange + cyclelength',
do=[OutputEvent('emit'), 'tchange=t'])),
])
ev_based_cc = ComponentClass(
name='EventBasedCurrentClass',
parameters=['dur', 'i'],
analog_ports=[SendPort('I')],
regimes=[
Regime(transitions=[
On('inputevent', do=['I=i', 'tchange = t']),
On('t>tchange + dur', do=['I=0', 'tchange=t'])
])
])
pulsing_emitter = ComponentClass(name='pulsing_cc',
subnodes={
'evs': emitter,
'cc': ev_based_cc
},
portconnections=[('evs.emit',
'cc.inputevent')])
nrn = ComponentClass(
name='LeakyNeuron',
parameters=['Cm', 'gL', 'E'],
regimes=[
Regime('dV/dt = (iInj + (E-V)*gL )/Cm'),
],
aliases=['iIn := iInj'],
analog_ports=[SendPort('V'),
ReducePort('iInj', reduce_op='+')],
)
combined_comp = ComponentClass(name='Comp1',
subnodes={
'nrn': nrn,
'cc1': pulsing_emitter,
'cc2': pulsing_emitter
},
portconnections=[
('cc1.cc.I', 'nrn.iInj'),
('cc2.cc.I', 'nrn.iInj')
])
combined_comp = flattening.flatten(combined_comp)
records = [
RecordValue(what='cc1_cc_I',
tag='Current',
label='Current Clamp 1'),
RecordValue(what='cc2_cc_I',
tag='Current',
label='Current Clamp 2'),
RecordValue(what='nrn_iIn',
tag='Current',
label='Total Input Current'),
RecordValue(what='nrn_V', tag='Voltage', label='Neuron Voltage'),
RecordValue(what='cc1_cc_tchange',
tag='Tchange',
label='tChange CC1'),
RecordValue(what='cc2_cc_tchange',
tag='Tchange',
label='tChange CC2'),
RecordValue(what='regime', tag='Regime', label='Regime'),
]
parameters = flattening.ComponentFlattener.flatten_namespace_dict({
'cc1.cc.i':
13.8,
'cc1.cc.dur':
10,
'cc1.evs.cyclelength':
30,
'cc2.cc.i':
20.8,
'cc2.cc.dur':
5.0,
'cc2.evs.cyclelength':
20,
'nrn.gL':
4.3,
'nrn.E':
-70
})
res = std_pynn_simulation(
test_component=combined_comp,
parameters=parameters,
initial_values={},
synapse_components=[],
records=records,
# plot = False,
)
return
t, records = res
def check_trace(trace_name, time_period, exp_mean, exp_std=0):
t_indices = (t > time_period[0] + 1) & (t < time_period[1] - 1)
self.assertAlmostEqual(records[trace_name][t_indices].mean(),
exp_mean,
places=3)
self.assertAlmostEqual(records[trace_name][t_indices].std(),
exp_std,
places=3)
check_trace('cc1_cc_I', (00, 30), exp_mean=0.0)
check_trace('cc1_cc_I', (30, 40), exp_mean=13.8)
check_trace('cc1_cc_I', (40, 60), exp_mean=0.0)
check_trace('cc1_cc_I', (60, 70), exp_mean=13.8)
check_trace('cc1_cc_I', (70, 90), exp_mean=0.0)
check_trace('cc1_cc_I', (90, 100), exp_mean=13.8)
check_trace('cc2_cc_I', (00, 20), exp_mean=0.0)
check_trace('cc2_cc_I', (20, 25), exp_mean=20.8)
check_trace('cc2_cc_I', (25, 40), exp_mean=0.0)
check_trace('cc2_cc_I', (40, 45), exp_mean=20.8)
check_trace('cc2_cc_I', (45, 60), exp_mean=0.0)
check_trace('cc2_cc_I', (60, 65), exp_mean=20.8)
check_trace('cc2_cc_I', (65, 80), exp_mean=0.0)
check_trace('cc2_cc_I', (80, 85), exp_mean=20.8)
check_trace('cc2_cc_I', (85, 100), exp_mean=0.0)
check_trace('nrn_iIn', (00, 20), exp_mean=0.0)
check_trace('nrn_iIn', (20, 25), exp_mean=20.8)
check_trace('nrn_iIn', (25, 30), exp_mean=0.0)
check_trace('nrn_iIn', (30, 40), exp_mean=13.8)
check_trace('nrn_iIn', (40, 45), exp_mean=20.8)
check_trace('nrn_iIn', (45, 60), exp_mean=0.0)
check_trace('nrn_iIn', (60, 65), exp_mean=34.6)
check_trace('nrn_iIn', (65, 70), exp_mean=13.8)
check_trace('nrn_iIn', (70, 80), exp_mean=0.0)
check_trace('nrn_iIn', (80, 85), exp_mean=20.8)
check_trace('nrn_iIn', (85, 90), exp_mean=0.0)
check_trace('nrn_iIn', (90, 100), exp_mean=13.8)
check_trace('nrn_V', (00 + 2, 20), exp_mean=(0.0 / 4.3) - 70)
check_trace('nrn_V', (20 + 2, 25), exp_mean=(20.8 / 4.3) - 70)
check_trace('nrn_V', (25 + 2, 30), exp_mean=(0.0 / 4.3) - 70)
check_trace('nrn_V', (30 + 2, 40), exp_mean=(13.8 / 4.3) - 70)
check_trace('nrn_V', (40 + 2, 45), exp_mean=(20.8 / 4.3) - 70)
check_trace('nrn_V', (45 + 2, 60), exp_mean=(0.0 / 4.3) - 70)
check_trace('nrn_V', (60 + 2, 65), exp_mean=(34.6 / 4.3) - 70)
check_trace('nrn_V', (65 + 2, 70), exp_mean=(13.8 / 4.3) - 70)
check_trace('nrn_V', (70 + 2, 80), exp_mean=(0.0 / 4.3) - 70)
check_trace('nrn_V', (80 + 2, 85), exp_mean=(20.8 / 4.3) - 70)
check_trace('nrn_V', (85 + 2, 90), exp_mean=(0.0 / 4.3) - 70)
check_trace('nrn_V', (90 + 2, 100), exp_mean=(13.8 / 4.3) - 70)
def get_compound_component():
"""Cannot yet be implemented in PyDSTool
"""
from nineml.abstraction_layer.testing_utils import RecordValue
from nineml.abstraction_layer import DynamicsClass, Regime, On, OutputEvent, AnalogSendPort, AnalogReducePort
emitter = DynamicsClass(
name='EventEmitter',
parameters=['cyclelength'],
regimes=[
Regime(transitions=On('t > tchange + cyclelength',
do=[OutputEvent('emit'), 'tchange=t'])),
])
ev_based_cc = DynamicsClass(
name='EventBasedCurrentClass',
parameters=['dur', 'i'],
analog_ports=[AnalogSendPort('I')],
regimes=[
Regime(transitions=[
On('inputevent', do=['I=i', 'tchange = t']),
On('t>tchange + dur', do=['I=0', 'tchange=t'])
])
])
pulsing_emitter = DynamicsClass(name='pulsing_cc',
subnodes={
'evs': emitter,
'cc': ev_based_cc
},
portconnections=[('evs.emit',
'cc.inputevent')])
nrn = DynamicsClass(
name='LeakyNeuron',
parameters=['Cm', 'gL', 'E'],
regimes=[
Regime('dV/dt = (iInj + (E-V)*gL )/Cm'),
],
aliases=['iIn := iInj'],
analog_ports=[
AnalogSendPort('V'),
AnalogReducePort('iInj', reduce_op='+')
],
)
combined_comp = DynamicsClass(name='Comp1',
subnodes={
'nrn': nrn,
'cc1': pulsing_emitter,
'cc2': pulsing_emitter
},
portconnections=[('cc1.cc.I', 'nrn.iInj'),
('cc2.cc.I', 'nrn.iInj')])
combined_comp = al.flattening.flatten(combined_comp)
## records = [
## RecordValue(what='cc1_cc_I', tag='Current', label='Current Clamp 1'),
## RecordValue(what='cc2_cc_I', tag='Current', label='Current Clamp 2'),
## RecordValue(what='nrn_iIn', tag='Current', label='Total Input Current'),
## RecordValue(what='nrn_V', tag='Voltage', label='Neuron Voltage'),
## RecordValue(what='cc1_cc_tchange', tag='Tchange', label='tChange CC1'),
## RecordValue(what='cc2_cc_tchange', tag='Tchange', label='tChange CC2'),
## RecordValue(what='regime', tag='Regime', label='Regime'),
## ]
parameters = al.flattening.ComponentFlattener.flatten_namespace_dict({
'cc1.cc.i':
13.8,
'cc1.cc.dur':
10,
'cc1.evs.cyclelength':
30,
'cc2.cc.i':
20.8,
'cc2.cc.dur':
5.0,
'cc2.evs.cyclelength':
20,
'nrn.gL':
4.3,
'nrn.E':
-70
})
return combined_comp, parameters
def test_Constructor(self):
d = ComponentClass(
name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime('dSV1/dt = -SV1/dp2', name='r1', transitions=On('input', 'SV1=SV1+1'))],
analog_ports=[RecvPort('dIn1'), SendPort('D1'), SendPort('D2')],
parameters=['dp1', 'dp2']
)
c = ComponentClass(
name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('emit')])],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[RecvPort('cIn1'), RecvPort('cIn2'), SendPort('C1'), SendPort('C2')],
parameters=['cp1', 'cp2']
)
# Test Cloner, no hierachy
# Everything should be as before:
c_clone = DynamicsClonerVisitorPrefixNamespace().visit(c)
self.assertEqual(c_clone.name, 'C')
self.assertEqual(set(c_clone.aliases_map.keys()), set(['C1', 'C2', 'C3']))
# - Regimes and Transitions:
self.assertEqual(set(c_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(len(list(c_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(c_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(c_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(c_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c_clone.regimes_map['r2'].on_conditions)), 1)
# - Ports & Parameters:
self.assertEqual(
set(c_clone.query.analog_ports_map.keys()), set(['cIn2', 'cIn1', 'C1', 'C2']))
self.assertEqual(set(c_clone.query.event_ports_map.keys()), set(['spikein', 'emit']))
self.assertEqual(set(c_clone.query.parameters_map.keys()), set(['cp1', 'cp2']))
self.assertEqual(set(c_clone.state_variables_map.keys()), set(['SV1']))
del c_clone
# Test Cloner, 1 level of hierachy
# Everything should be as before:
b = ComponentClass(name='B',
subnodes={'c1': c, 'c2': c},
portconnections=[('c1.C1', 'c2.cIn1'), ('c2.emit', 'c1.spikein'), ])
b_clone = DynamicsClonerVisitorPrefixNamespace().visit(b)
c1_clone = b_clone.get_subnode('c1')
c2_clone = b_clone.get_subnode('c2')
self.assertEqual(c1_clone.name, 'C')
self.assertEqual(c2_clone.name, 'C')
self.assertEqual(set(c1_clone.aliases_map.keys()), set(['c1_C1', 'c1_C2', 'c1_C3']))
self.assertEqual(set(c2_clone.aliases_map.keys()), set(['c2_C1', 'c2_C2', 'c2_C3']))
# - Regimes and Transitions:
self.assertEqual(set(c1_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(len(list(c1_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(c1_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(c1_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(c1_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c1_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(set(c2_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(len(list(c2_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(c2_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(c2_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(c2_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c2_clone.regimes_map['r2'].on_conditions)), 1)
# - Ports & Parameters:
self.assertEqual(
set(c1_clone.query.analog_ports_map.keys()),
set(['c1_cIn1', 'c1_cIn2', 'c1_C1', 'c1_C2']))
self.assertEqual(
set(c2_clone.query.analog_ports_map.keys()),
set(['c2_cIn1', 'c2_cIn2', 'c2_C1', 'c2_C2']))
self.assertEqual(set(c1_clone.query.event_ports_map.keys()),
set(['c1_spikein', 'c1_emit']))
self.assertEqual(set(c2_clone.query.event_ports_map.keys()),
set(['c2_spikein', 'c2_emit']))
self.assertEqual(
set(c1_clone.query.parameters_map.keys()),
set(['c1_cp1', 'c1_cp2']))
self.assertEqual(
set(c2_clone.query.parameters_map.keys()),
set(['c2_cp1', 'c2_cp2']))
self.assertEqual(
set(c1_clone.state_variables_map.keys()),
set(['c1_SV1']))
self.assertEqual(
set(c2_clone.state_variables_map.keys()),
set(['c2_SV1']))
# - Port Connections:
self.assertEqual(
set(b_clone.portconnections),
set([(NSA('c1.c1_C1'), NSA('c2.c2_cIn1')),
(NSA('c2.c2_emit'), NSA('c1.c1_spikein'))])
)
del b_clone
del c1_clone
del c2_clone
# Two Levels of nesting:
a = ComponentClass(name='A',
subnodes={'b1': b, 'b2': b, 'c3': c},
portconnections=[
('b1.c1.emit', 'c3.spikein'),
('c3.C2', 'b1.c2.cIn2')
]
)
a_clone = DynamicsClonerVisitorPrefixNamespace().visit(a)
b1_clone = a_clone.get_subnode('b1')
b2_clone = a_clone.get_subnode('b2')
b1c1_clone = a_clone.get_subnode('b1.c1')
b1c2_clone = a_clone.get_subnode('b1.c2')
b2c1_clone = a_clone.get_subnode('b2.c1')
b2c2_clone = a_clone.get_subnode('b2.c2')
c3_clone = a_clone.get_subnode('c3')
clones = [b1_clone,
b2_clone,
b1c1_clone,
b1c2_clone,
b2c1_clone,
b2c2_clone,
c3_clone, ]
# Check for duplicates:
self.assertEquals(len(clones), len(set(clones)))
# Names:
self.assertEqual(b1_clone.name, 'B')
self.assertEqual(b2_clone.name, 'B')
self.assertEqual(b1c1_clone.name, 'C')
self.assertEqual(b1c2_clone.name, 'C')
self.assertEqual(c3_clone.name, 'C')
self.assertEqual(b2c1_clone.name, 'C')
self.assertEqual(b2c2_clone.name, 'C')
# Aliases:
self.assertEqual(set(b1_clone.aliases_map.keys()), set([]))
self.assertEqual(set(b2_clone.aliases_map.keys()), set([]))
self.assertEqual(set(b1c1_clone.aliases_map.keys()), set(
['b1_c1_C1', 'b1_c1_C2', 'b1_c1_C3']))
self.assertEqual(set(b1c2_clone.aliases_map.keys()), set(
['b1_c2_C1', 'b1_c2_C2', 'b1_c2_C3']))
self.assertEqual(set(b2c1_clone.aliases_map.keys()), set(
['b2_c1_C1', 'b2_c1_C2', 'b2_c1_C3']))
self.assertEqual(set(b2c2_clone.aliases_map.keys()), set(
['b2_c2_C1', 'b2_c2_C2', 'b2_c2_C3']))
self.assertEqual(set(c3_clone.aliases_map.keys()), set(['c3_C1', 'c3_C2', 'c3_C3']))
# Regimes:
self.assertEqual(set(b1_clone.regimes_map.keys()), set([]))
self.assertEqual(set(b2_clone.regimes_map.keys()), set([]))
self.assertEqual(set(b1c1_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(set(b1c2_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(set(b2c1_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(set(b2c2_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(set(c3_clone.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(len(list(b1c1_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(b1c1_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(b1c1_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(b1c1_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(b1c1_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(b1c2_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(b1c2_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(b1c2_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(b1c2_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(b1c2_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(b2c1_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(b2c1_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(b2c1_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(b2c1_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(b2c1_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(b2c2_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(b2c2_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(b2c2_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(b2c2_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(b2c2_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c3_clone.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(c3_clone.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(c3_clone.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(c3_clone.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c3_clone.regimes_map['r2'].on_conditions)), 1)
# Ports, params and state-vars:
# c1:
self.assertEqual(set(b1c1_clone.query.analog_ports_map.keys()), set(
['b1_c1_cIn1', 'b1_c1_cIn2', 'b1_c1_C1', 'b1_c1_C2']))
self.assertEqual(
set(b1c1_clone.query.event_ports_map.keys()), set(['b1_c1_spikein', 'b1_c1_emit']))
self.assertEqual(
set(b1c1_clone.query.parameters_map.keys()), set(['b1_c1_cp1', 'b1_c1_cp2']))
self.assertEqual(set(b1c1_clone.state_variables_map.keys()), set(['b1_c1_SV1']))
self.assertEqual(set(b1c2_clone.query.analog_ports_map.keys()), set(
['b1_c2_cIn1', 'b1_c2_cIn2', 'b1_c2_C1', 'b1_c2_C2']))
self.assertEqual(
set(b1c2_clone.query.event_ports_map.keys()), set(['b1_c2_spikein', 'b1_c2_emit']))
self.assertEqual(
set(b1c2_clone.query.parameters_map.keys()), set(['b1_c2_cp1', 'b1_c2_cp2']))
self.assertEqual(set(b1c2_clone.state_variables_map.keys()), set(['b1_c2_SV1']))
self.assertEqual(set(b2c1_clone.query.analog_ports_map.keys()),
set(['b2_c1_cIn1', 'b2_c1_cIn2', 'b2_c1_C1', 'b2_c1_C2']))
self.assertEqual(
set(b2c1_clone.query.event_ports_map.keys()), set(['b2_c1_spikein', 'b2_c1_emit']))
self.assertEqual(
set(b2c1_clone.query.parameters_map.keys()), set(['b2_c1_cp1', 'b2_c1_cp2']))
self.assertEqual(set(b2c1_clone.state_variables_map.keys()), set(['b2_c1_SV1']))
self.assertEqual(set(b2c2_clone.query.analog_ports_map.keys()), set(
['b2_c2_cIn1', 'b2_c2_cIn2', 'b2_c2_C1', 'b2_c2_C2']))
self.assertEqual(
set(b2c2_clone.query.event_ports_map.keys()), set(['b2_c2_spikein', 'b2_c2_emit']))
self.assertEqual(
set(b2c2_clone.query.parameters_map.keys()), set(['b2_c2_cp1', 'b2_c2_cp2']))
self.assertEqual(set(b2c2_clone.state_variables_map.keys()), set(['b2_c2_SV1']))
self.assertEqual(set(c3_clone.query.analog_ports_map.keys()), set(
['c3_cIn1', 'c3_cIn2', 'c3_C1', 'c3_C2']))
self.assertEqual(
set(c3_clone.query.event_ports_map.keys()), set(['c3_spikein', 'c3_emit']))
self.assertEqual(
set(c3_clone.query.parameters_map.keys()), set(['c3_cp1', 'c3_cp2']))
self.assertEqual(set(c3_clone.state_variables_map.keys()), set(['c3_SV1']))
self.assertEqual(set(b1_clone.query.analog_ports_map.keys()), set([]))
self.assertEqual(set(b1_clone.query.event_ports_map.keys()), set([]))
self.assertEqual(set(b1_clone.query.parameters_map.keys()), set([]))
self.assertEqual(set(b1_clone.state_variables_map.keys()), set([]))
self.assertEqual(set(b2_clone.query.analog_ports_map.keys()), set([]))
self.assertEqual(set(b2_clone.query.event_ports_map.keys()), set([]))
self.assertEqual(set(b2_clone.query.parameters_map.keys()), set([]))
self.assertEqual(set(b2_clone.state_variables_map.keys()), set([]))
# Port Connections
self.assertEqual(
set(b1_clone.portconnections),
set([
(NSA('c1.b1_c1_C1'), NSA('c2.b1_c2_cIn1')),
(NSA('c2.b1_c2_emit'), NSA('c1.b1_c1_spikein')),
])
)
self.assertEqual(
set(b2_clone.portconnections),
set([
(NSA('c1.b2_c1_C1'), NSA('c2.b2_c2_cIn1')),
(NSA('c2.b2_c2_emit'), NSA('c1.b2_c1_spikein')),
])
)
self.assertEqual(
set(a_clone.portconnections),
set([
(NSA('b1.c1.b1_c1_emit'), NSA('c3.c3_spikein')),
(NSA('c3.c3_C2'), NSA('b1.c2.b1_c2_cIn2')),
])
)
def test_Flattening4(self):
c = ComponentClass(
name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1', 'C4:=cIn2'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(
name='D',
aliases=['D1:=dp1', 'D2 := dIn1 + dp2', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Test Cloner, 2 levels of hierachy
# ------------------------------ #
# Everything should be as before:
b = ComponentClass(
name='B',
subnodes={
'c1': c,
'c2': c,
'd': d
},
portconnections=[('c1.C1', 'c2.cIn2'), ('c2.C1', 'c1.cIn1')],
)
a = ComponentClass(name='A',
subnodes={
'b': b,
'c': c
},
portconnections=[('b.c1.C1', 'b.c1.cIn2'),
('b.c1.C1', 'b.c2.cIn1'),
('b.c1.C2', 'b.d.dIn1')])
a_flat = flattening.flatten(a)
# Name
self.assertEqual(a_flat.name, 'A')
# Aliases
self.assertEqual(
set(a_flat.aliases_map.keys()),
set([
'b_c1_C1', 'b_c1_C2', 'b_c1_C3', 'b_c1_C4', 'b_c2_C1',
'b_c2_C2', 'b_c2_C3', 'b_c2_C4', 'b_d_D1', 'b_d_D2', 'b_d_D3',
'c_C1', 'c_C2', 'c_C3', 'c_C4'
]))
# - Regimes and Transitions:
self.assertEqual(len(a_flat.regimes_map), 16)
r_c1_1_c2_1_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r1 c:r1')
r_c1_1_c2_2_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r2 c:r1')
r_c1_2_c2_1_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r1 c:r1')
r_c1_2_c2_2_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r2 c:r1')
r_c1_1_c2_1_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r1 c:r1')
r_c1_1_c2_2_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r2 c:r1')
r_c1_2_c2_1_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r1 c:r1')
r_c1_2_c2_2_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r2 c:r1')
r_c1_1_c2_1_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r1 c:r2')
r_c1_1_c2_2_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r2 c:r2')
r_c1_2_c2_1_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r1 c:r2')
r_c1_2_c2_2_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r2 c:r2')
r_c1_1_c2_1_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r1 c:r2')
r_c1_1_c2_2_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r2 c:r2')
r_c1_2_c2_1_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r1 c:r2')
r_c1_2_c2_2_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r2 c:r2')
regimes = [
r_c1_1_c2_1_d_1_c_1, r_c1_1_c2_2_d_1_c_1, r_c1_2_c2_1_d_1_c_1,
r_c1_2_c2_2_d_1_c_1, r_c1_1_c2_1_d_2_c_1, r_c1_1_c2_2_d_2_c_1,
r_c1_2_c2_1_d_2_c_1, r_c1_2_c2_2_d_2_c_1, r_c1_1_c2_1_d_1_c_2,
r_c1_1_c2_2_d_1_c_2, r_c1_2_c2_1_d_1_c_2, r_c1_2_c2_2_d_1_c_2,
r_c1_1_c2_1_d_2_c_2, r_c1_1_c2_2_d_2_c_2, r_c1_2_c2_1_d_2_c_2,
r_c1_2_c2_2_d_2_c_2
]
self.assertEqual(len(set(regimes)), 16)
# Do we have the right number of on_events and on_conditions:
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_1.on_events)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_1.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_2.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_2.on_events)), 0)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_2.on_conditions)), 4)
# All on_events return to thier same transition:
for r in a_flat.regimes:
for on_ev in r.on_events:
self.assertEquals(on_ev.target_regime, r)
# Check On-Event port names are remapped properly:
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1_c_1.on_events]),
set(['c_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1_c_1.on_events]),
set(['c_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2_c_1.on_events]),
set([
'c_spikein',
'b_c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2_c_1.on_events]),
set([
'c_spikein',
'b_c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2_c_1.on_events]),
set(['c_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1_c_2.on_events]),
set(['b_c1_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1_c_2.on_events]),
set(['b_c1_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1_c_2.on_events]),
set(['b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1_c_2.on_events]),
set(['b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2_c_2.on_events]),
set(['b_c1_spikein', 'b_c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2_c_2.on_events]),
set([
'b_c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2_c_2.on_events]),
set([
'b_c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2_c_2.on_events]),
set([]))
# ToDo: Check the OnConditions:
# - Ports & Parameters:
self.assertEqual(
set(a_flat.query.analog_ports_map.keys()),
set([
'b_c1_C1', 'b_c1_C2', 'b_c2_C1', 'b_c2_C2', 'b_d_dIn2',
'b_d_D1', 'b_d_D2', 'c_cIn1', 'c_cIn2', 'c_C1', 'c_C2'
]))
self.assertEqual(
set(a_flat.query.event_ports_map.keys()),
set([
'b_c1_spikein',
'b_c1_emit',
'b_c1_c_emit',
'b_c2_spikein',
'b_c2_emit',
'b_c2_c_emit',
'b_d_spikein',
'b_d_emit',
'b_d_d_emit',
'c_spikein',
'c_emit',
'c_c_emit',
]))
self.assertEqual(
set(a_flat.query.parameters_map.keys()),
set([
'c_cp1',
'c_cp2',
'b_c1_cp1',
'b_c1_cp2',
'b_c2_cp1',
'b_c2_cp2',
'b_d_dp1',
'b_d_dp2',
]))
self.assertEqual(set(a_flat.state_variables_map.keys()),
set(['b_c1_SV1', 'b_c2_SV1', 'b_d_SV1', 'c_SV1']))
# Back-sub everything - then do we get the correct port mappings:
a_flat.backsub_all()
self.assertEqual(set(a_flat.aliases_map['b_c2_C4'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c1_C2'].rhs_atoms),
set(['b_c2_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c1_C4'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c2_C2'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_d_D2'].rhs_atoms),
set(['b_c2_cp1', 'b_d_dp2']))
def test_Flattening1(self):
c = ComponentClass(name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Flatten a flat component
# Everything should be as before:
c_flat = flattening.flatten(c)
assert c_flat is not c
self.assertEqual(c_flat.name, 'C')
self.assertEqual(set(c_flat.aliases_map.keys()),
set(['C1', 'C2', 'C3']))
# - Regimes and Transitions:
self.assertEqual(set(c_flat.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(len(list(c_flat.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_conditions)), 1)
# - Ports & Parameters:
self.assertEqual(set(c_flat.query.analog_ports_map.keys()),
set(['cIn2', 'cIn1', 'C1', 'C2']))
self.assertEqual(set(c_flat.query.event_ports_map.keys()),
set(['spikein', 'c_emit', 'emit']))
self.assertEqual(set(c_flat.query.parameters_map.keys()),
set(['cp1', 'cp2']))
self.assertEqual(set(c_flat.state_variables_map.keys()), set(['SV1']))
def test_regimes(self):
c = ComponentClass(name='cl', )
self.assertEqual(len(list(c.regimes)), 0)
c = ComponentClass(name='cl',
regimes=Regime('dX/dt=0',
name='r1',
transitions=On('X>X1',
do=['X = X0'],
to=None)))
self.assertEqual(len(list(c.regimes)), 1)
c = ComponentClass(name='cl',
regimes=[
Regime('dX/dt=0',
name='r1',
transitions=On('X>X1',
do=['X=X0'],
to='r2')),
Regime('dX/dt=0',
name='r2',
transitions=On('X>X1',
do=['X=X0'],
to='r3')),
Regime('dX/dt=0',
name='r3',
transitions=On('X>X1',
do=['X=X0'],
to='r4')),
Regime('dX/dt=0',
name='r4',
transitions=On('X>X1',
do=['X=X0'],
to='r1')),
])
self.assertEqual(len(list(c.regimes)), 4)
self.assertEqual(set(c.regimes_map.keys()),
set(['r1', 'r2', 'r3', 'r4']))
c = ComponentClass(
name='cl',
dynamicsblock=DynamicsBlock(regimes=[
Regime('dX/dt=0',
name='r1',
transitions=On('X>X1', do=['X=X0'], to='r2')),
Regime('dX/dt=0',
name='r2',
transitions=On('X>X1', do=['X=X0'], to='r3')),
Regime('dX/dt=0',
name='r3',
transitions=On('X>X1', do=['X=X0'], to='r4')),
Regime('dX/dt=0',
name='r4',
transitions=On('X>X1', do=['X=X0'], to='r1')),
]))
self.assertEqual(len(list(c.regimes)), 4)
self.assertEqual(set([r.name for r in c.regimes]),
set(['r1', 'r2', 'r3', 'r4']))
# Duplicate Names:
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='cl',
regimes=[
Regime('dX/dt=0',
name='r',
transitions=On('X>X1', do=['X=X0'])),
Regime('dX/dt=0',
name='r',
transitions=On(
'X>X1',
do=['X=X0'],
)),
])
def test_Flattening2(self):
c = ComponentClass(name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Test Cloner, 1 level of hierachy
# ------------------------------ #
# Everything should be as before:
b = ComponentClass(
name='B',
subnodes={
'c1': c,
'c2': c,
'd': d
},
# portconnections= [('c1.C1','c2.cIn1'),('c2.emit','c1.spikein'), ]
)
b_flat = flattening.flatten(b)
# Name
self.assertEqual(b_flat.name, 'B')
# Aliases
self.assertEqual(
set(b_flat.aliases_map.keys()),
set([
'c1_C1', 'c1_C2', 'c1_C3', 'c2_C1', 'c2_C2', 'c2_C3', 'd_D1',
'd_D2', 'd_D3'
]))
# - Regimes and Transitions:
self.assertEqual(len(b_flat.regimes_map), 8)
r_c1_1_c2_1_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r1 c2:r1 ')
r_c1_1_c2_2_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r1 c2:r2 ')
r_c1_2_c2_1_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r2 c2:r1')
r_c1_2_c2_2_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r2 c2:r2')
r_c1_1_c2_1_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r1 c2:r1 ')
r_c1_1_c2_2_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r1 c2:r2 ')
r_c1_2_c2_1_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r2 c2:r1')
r_c1_2_c2_2_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r2 c2:r2')
# Do we have the right number of on_events and on_conditions:
self.assertEqual(len(list(r_c1_1_c2_1_d_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_1.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_2_d_1.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_1_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_2.on_events)), 1)
self.assertEqual(len(list(r_c1_1_c2_2_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_1_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_2_d_2.on_events)), 0)
self.assertEqual(len(list(r_c1_2_c2_2_d_2.on_conditions)), 3)
# All on_events return to thier same transition:
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[0].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[1].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[2].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_2_d_1.on_events))[0].target_regime,
r_c1_1_c2_2_d_1)
self.assertEqual((list(r_c1_1_c2_2_d_1.on_events))[1].target_regime,
r_c1_1_c2_2_d_1)
self.assertEqual((list(r_c1_2_c2_1_d_1.on_events))[0].target_regime,
r_c1_2_c2_1_d_1)
self.assertEqual((list(r_c1_2_c2_1_d_1.on_events))[1].target_regime,
r_c1_2_c2_1_d_1)
self.assertEqual((list(r_c1_2_c2_2_d_1.on_events))[0].target_regime,
r_c1_2_c2_2_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_2.on_events))[0].target_regime,
r_c1_1_c2_1_d_2)
self.assertEqual((list(r_c1_1_c2_1_d_2.on_events))[1].target_regime,
r_c1_1_c2_1_d_2)
self.assertEqual((list(r_c1_1_c2_2_d_2.on_events))[0].target_regime,
r_c1_1_c2_2_d_2)
self.assertEqual((list(r_c1_2_c2_1_d_2.on_events))[0].target_regime,
r_c1_2_c2_1_d_2)
# Check On-Event port names are remapped properly:
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1.on_events]),
set(['c1_spikein', 'c2_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1.on_events]),
set(['c1_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1.on_events]),
set(['c2_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1.on_events]),
set(['d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2.on_events]),
set(['c1_spikein', 'c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2.on_events]),
set([
'c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2.on_events]),
set([
'c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2.on_events]),
set([]))
# ToDo: Check the OnConditions:
# - Ports & Parameters:
self.assertEqual(
set(b_flat.query.analog_ports_map.keys()),
set([
'c1_cIn1', 'c1_cIn2', 'c1_C1', 'c1_C2', 'c2_cIn1', 'c2_cIn2',
'c2_C1', 'c2_C2', 'd_dIn1', 'd_dIn2', 'd_D1', 'd_D2'
]))
self.assertEqual(
set(b_flat.query.event_ports_map.keys()),
set([
'c1_spikein', 'c1_emit', 'c1_c_emit', 'c2_spikein', 'c2_emit',
'c2_c_emit', 'd_spikein', 'd_emit', 'd_d_emit'
]))
self.assertEqual(
set(b_flat.query.parameters_map.keys()),
set([
'c1_cp1',
'c1_cp2',
'c2_cp1',
'c2_cp2',
'd_dp1',
'd_dp2',
]))
self.assertEqual(set(b_flat.state_variables_map.keys()),
set(['c1_SV1', 'c2_SV1', 'd_SV1']))
def test_event_send_recv_ports(self):
# Signature: name(self)
# Get the ``recv`` EventPorts
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
# Check inference of output event ports:
c = ComponentClass(
name='Comp1',
regimes=Regime(transitions=[
On('in_ev1', do=OutputEvent('ev_port1')),
On('V < b', do=OutputEvent('ev_port1')),
On('V < c', do=OutputEvent('ev_port2')),
]),
)
self.assertEquals(len(c.query.event_recv_ports), 1)
self.assertEquals((list(c.query.event_recv_ports)[0]).name, 'in_ev1')
self.assertEquals(len(c.query.event_send_ports), 2)
self.assertEquals((list(c.query.event_send_ports)[0]).name, 'ev_port1')
self.assertEquals((list(c.query.event_send_ports)[1]).name, 'ev_port2')
# Check inference of output event ports:
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('V > a',
do=OutputEvent('ev_port1'),
to='r2'),
On('in_ev1',
do=OutputEvent('ev_port2')),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2'),
to='r1'),
On('in_ev2',
do=OutputEvent('ev_port3')),
])
])
self.assertEquals(len(c.query.event_recv_ports), 2)
self.assertEquals((list(c.query.event_recv_ports)[0]).name, 'in_ev1')
self.assertEquals((list(c.query.event_recv_ports)[1]).name, 'in_ev2')
self.assertEquals(len(c.query.event_send_ports), 3)
self.assertEquals((list(c.query.event_send_ports)[0]).name, 'ev_port1')
self.assertEquals((list(c.query.event_send_ports)[1]).name, 'ev_port2')
self.assertEquals((list(c.query.event_send_ports)[2]).name, 'ev_port3')
# Check inference of output event ports:
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2',
do=[
OutputEvent('ev_port1'),
OutputEvent('ev_port2')
],
to='r2'),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2')),
On('spikeinput3',
do=OutputEvent('ev_port3'),
to='r1'),
])
])
self.assertEquals(len(c.query.event_recv_ports), 3)
self.assertEquals((list(c.query.event_recv_ports)[0]).name,
'spikeinput1')
self.assertEquals((list(c.query.event_recv_ports)[1]).name,
'spikeinput2')
self.assertEquals((list(c.query.event_recv_ports)[2]).name,
'spikeinput3')
self.assertEquals(len(c.query.event_send_ports), 3)
self.assertEquals((list(c.query.event_send_ports)[0]).name, 'ev_port1')
self.assertEquals((list(c.query.event_send_ports)[1]).name, 'ev_port2')
self.assertEquals((list(c.query.event_send_ports)[2]).name, 'ev_port3')