def to_verilog(dut_mod, **kw_args):
#alu = Alu(8)
#main(alu,
# ports
# =[
# alu.bus.a, alu.bus.b, alu.bus.carry_in, alu.bus.op,
# alu.bus.result, alu.bus.carry_out
# ])
dut = dut_mod(**kw_args)
main(dut, ports=dut.bus().ports())
m = Module()
m.submodules.ext_port = self.ext_port
m.submodules.mem_rdport = mem_rdport = self.memory.read_port(
transparent=False)
m.submodules.mem_wrport = mem_wrport = self.memory.write_port()
m.submodules.core = BonelessCoreFSM(reset_addr=8,
mem_rdport=mem_rdport,
mem_wrport=mem_wrport,
ext_port=self.ext_port)
return m.lower(platform)
def simulate():
uut = CPU()
frag = uut.get_fragment(None)
with pysim.Simulator(frag, vcd_file=open('cpu.vcd', 'w')) as sim:
sim.add_clock(1 / 16e6, domain='sync')
sim.run_until(1 / 16e6 * 10000, run_passive=True)
if __name__ == '__main__':
#simulate()
cpu = CPU()
main(cpu,
name='cpu',
ports=[cpu.ext_port.db, cpu.ext_port.rs, cpu.ext_port.e])
#!/usr/bin/env python3
from nmigen import *
from nmigen.cli import main
m = Module()
cd_por = ClockDomain(reset_less=True)
cd_sync = ClockDomain()
m.domains += cd_por, cd_sync
delay = Signal(range(256), reset=255)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
m.d.comb += [
ClockSignal().eq(cd_por.clk),
ResetSignal().eq(delay != 0),
]
if __name__ == "__main__":
main(m, ports=[cd_por.clk])
from nmigen import *
from nmigen.cli import main
m = Module()
cd_por = ClockDomain(reset_less=True)
cd_sync = ClockDomain()
m.domains += cd_por, cd_sync
delay = Signal(max=255, reset=255)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
m.d.comb += [
ClockSignal().eq(cd_por.clk),
ResetSignal().eq(delay == 0),
]
if __name__ == "__main__":
main(m, ports=[cd_por.clk])
from nmigen import *
from nmigen.cli import main
class System:
def __init__(self):
self.adr = Signal(16)
self.dat_r = Signal(8)
self.dat_w = Signal(8)
self.we = Signal()
def elaborate(self, platform):
m = Module()
m.submodules.cpu = Instance("CPU",
p_RESET_ADDR=0xfff0,
i_d_adr =self.adr,
i_d_dat_r=self.dat_r,
o_d_dat_w=self.dat_w,
i_d_we =self.we,
)
return m
if __name__ == "__main__":
sys = System()
main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we])
def __init__(self, stretch=500):
self.o = Signal()
self.stretch = stretch
def elaborate(self, platform):
m = Module()
fader = Fade()
onoff = OnOff(stretch=self.stretch)
m.d.sync += fader.active.eq(onoff.o)
m.d.comb += self.o.eq(fader.o)
m.submodules.fader = fader
m.submodules.onoff = onoff
return m
if __name__ == "__main__":
# b = Larson(width=4, stretch=50)
# pins = (b.track, b.stretcher, b.stretch, b.updown)
# main(b, pins, name="top")
# f = Fade()
# pins = (f.o,f.active,f.counter,f.value,f.enable)
# main(f,pins,name="top")
# c = OnOff(stretch=500)
# pins = (c.o,c.stretch,c.stretcher)
# main(c,pins,name="top")
f = FadeTest(stretch=4000)
pins = f.o
main(f, pins, name="fader")
from nmigen import *
from nmigen.cli import main
class ParMux(Elaboratable):
def __init__(self, width):
self.s = Signal(3)
self.a = Signal(width)
self.b = Signal(width)
self.c = Signal(width)
self.o = Signal(width)
def elaborate(self, platform):
m = Module()
with m.Switch(self.s):
with m.Case("--1"):
m.d.comb += self.o.eq(self.a)
with m.Case("-1-"):
m.d.comb += self.o.eq(self.b)
with m.Case("1--"):
m.d.comb += self.o.eq(self.c)
with m.Case():
m.d.comb += self.o.eq(0)
return m
if __name__ == "__main__":
pmux = ParMux(width=16)
main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o])
m = Module()
m.submodules.top_module = top = self.top
s_end = Signal(1)
# master interface
m.d.comb += [
self.m_tdata.eq(top.data_out),
self.m_tlast.eq(top.end_out),
top.busy_in.eq(self.m_tready == 0),
self.m_tvalid.eq(top.valid_out),
]
# slave interface
m.d.comb += [
top.pixel_in1.eq(self.s_tdata[20:32]),
top.pixel_in2.eq(self.s_tdata[8:20]),
self.s_tready.eq(top.nready == 0),
s_end.eq(self.s_tlast),
top.valid_in.eq(self.s_tvalid),
]
return m
if __name__ == "__main__":
d = BetaIntegrationAxiStream()
main(d, ports=d.ios)
self.predics_out, lbuffs[i])
]
with m.Else():
with m.Switch(buff_ctr):
for i in range(self.gb):
with m.Case(i):
m.d.sync += [
predic_out.eq(buff)
for predic_out, buff in zip(
self.predics_out, buffs[i])
]
#if valid data
m.d.sync += self.valid_out.eq(self.valid_in)
# end
m.d.sync += self.end_out.eq(self.end_in)
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 2,
"predictor_function": 1,
"num_of_components": 4,
}
p = PredictorP1C4Pix12(config, constraints.Constraints())
main(p, ports=p.ios)
def delay(d):
for _ in range(d):
yield None
def generate_signals(gen):
with m.Switch(cycle+1):
c = 0
ss = []
for s in gen():
if s is not None:
ss.append([s])
continue
c += 1
ss = list(itertools.chain(*ss)) # Flatten list
if len(ss) > 0:
with m.Case(c):
m.d.pos += ss
ss = []
def signal_generator():
yield from delay(3)
yield rst.eq(0)
yield [unf_in.eq(0)]
yield from delay(1)
generate_signals(signal_generator)
m.d.comb += Cover(cycle == 10)
main(m, ports=[clk, rst, edgelord.clk_state, edgelord.unf_in, edgelord.unf_out])
from nmigen import *
from nmigen.cli import main
class ALU(Elaboratable):
def __init__(self, width):
self.sel = Signal(2)
self.a = Signal(width)
self.b = Signal(width)
self.o = Signal(width)
self.co = Signal()
def elaborate(self, platform):
m = Module()
with m.If(self.sel == 0b00):
m.d.comb += self.o.eq(self.a | self.b)
with m.Elif(self.sel == 0b01):
m.d.comb += self.o.eq(self.a & self.b)
with m.Elif(self.sel == 0b10):
m.d.comb += self.o.eq(self.a ^ self.b)
with m.Else():
m.d.comb += Cat(self.o, self.co).eq(self.a - self.b)
return m
if __name__ == "__main__":
alu = ALU(width=16)
main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co])
i_S_AXI_ACLK=ClockSignal(self.domain),
i_S_AXI_ARESETN=~ResetSignal(self.domain),
**self.get_instance_ports(),
)
if isinstance(platform, Platform):
for d in self.DEPENDENCIES:
add_verilog_file(platform, d)
return m
if __name__ == '__main__':
from nmigen.cli import main
xbar = AxiLiteXBar(32, 16)
slave1 = AxiLiteSlave(32, 16, name='slave1')
slave2 = AxiLiteSlave(32, 16, name='slave2')
master1 = AxiLiteMaster(32, 16, name='master1')
master2 = AxiLiteMaster(32, 16, name='master2')
xbar.add_slave(slave1, 0x8000, 0x1000)
xbar.add_slave(slave2, 0x9000, 0x1000)
xbar.add_master(master1)
xbar.add_master(master2)
ports = [v for v in slave1.fields.values()]
ports += [v for v in slave2.fields.values()]
ports += [v for v in master1.fields.values()]
ports += [v for v in master2.fields.values()]
main(xbar, None, ports=ports)
('TVALID', 1, Direction.FANOUT),
('TREADY', 1, Direction.FANIN),
('TLAST', 1, Direction.FANOUT)]
Record.__init__(self, layout, name=name, fields=fields)
class DummyCore(Elaboratable):
def __init__(self, width, testcase):
self.input = AxiStream(width, 'sink', name='INPUT')
self.output = AxiStream(width, 'source', name='OUTPUT')
self.testcase = int(testcase)
def elaborate(self, platform):
m = Module()
comb = m.d.comb
if self.testcase == 0:
comb += self.output.connect(self.input) # does not connect the signals
elif self.testcase == 1:
comb += self.input.connect(self.output) # does not connect the signals
else:
comb += self.output.TDATA.eq(self.input.TDATA)
comb += self.output.TVALID.eq(self.input.TVALID)
comb += self.output.TLAST.eq(self.input.TLAST)
comb += self.input.TREADY.eq(self.output.TREADY)
return m
if __name__ == '__main__':
testcase = os.environ['TESTCASE']
top = DummyCore(16, testcase)
ports = [top.input[f] for f in top.input.fields]
ports += [top.output[f] for f in top.output.fields]
main(top, ports=ports)
from nmigen import *
from nmigen.cli import main
pin = Signal()
pin_t = TSTriple()
m = Module()
m.submodules += pin_t.get_tristate(pin)
if __name__ == "__main__":
main(m, ports=[pin, pin_t.oe, pin_t.i, pin_t.o])
from nmigen import *
from nmigen.cli import main
class ALU:
def __init__(self, width):
self.sel = Signal(2)
self.a = Signal(width)
self.b = Signal(width)
self.o = Signal(width)
self.co = Signal()
def elaborate(self, platform):
m = Module()
with m.If(self.sel == 0b00):
m.d.comb += self.o.eq(self.a | self.b)
with m.Elif(self.sel == 0b01):
m.d.comb += self.o.eq(self.a & self.b)
with m.Elif(self.sel == 0b10):
m.d.comb += self.o.eq(self.a ^ self.b)
with m.Else():
m.d.comb += Cat(self.o, self.co).eq(self.a - self.b)
return m
if __name__ == "__main__":
alu = ALU(width=16)
main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co])
from nmigen import *
from nmigen.cli import main
class RegisterFile:
def __init__(self):
self.adr = Signal(4)
self.dat_r = Signal(8)
self.dat_w = Signal(8)
self.we = Signal()
self.mem = Memory(width=8, depth=16, init=[0xaa, 0x55])
def elaborate(self, platform):
m = Module()
m.submodules.rdport = rdport = self.mem.read_port()
m.submodules.wrport = wrport = self.mem.write_port()
m.d.comb += [
rdport.addr.eq(self.adr),
self.dat_r.eq(rdport.data),
wrport.addr.eq(self.adr),
wrport.data.eq(self.dat_w),
wrport.en.eq(self.we),
]
return m
if __name__ == "__main__":
rf = RegisterFile()
main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we])
from nmigen import *
from nmigen.lib.cdc import FFSynchronizer
from nmigen.cli import main
i, o = Signal(name="i"), Signal(name="o")
m = Module()
m.submodules += FFSynchronizer(i, o)
if __name__ == "__main__":
main(m, ports=[i, o])
#!/usr/bin/env python3
from nmigen import *
from nmigen.cli import main
class ClockDivisor(Elaboratable):
def __init__(self, factor):
self.v = Signal(factor)
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m
if __name__ == "__main__":
m = Module()
m.domains.sync = sync = ClockDomain("sync", async_reset=True)
m.submodules.ctr = ctr = ClockDivisor(factor=16)
main(m, ports=[ctr.o, sync.clk])
from nmigen import *
from nmigen.cli import main
pin = Signal()
pin_t = TSTriple()
m = Module()
m.submodules += pin_t.get_tristate(pin)
if __name__ == "__main__":
main(m, ports=[pin, pin_t.oe, pin_t.i, pin_t.o])
from nmigen import *
from nmigen.cli import main
class ClockDivisor(Elaboratable):
def __init__(self, factor):
self.v = Signal(factor)
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m
if __name__ == "__main__":
ctr = ClockDivisor(factor=16)
m = ctr.elaborate(platform=None)
m.domains += ClockDomain("sync", async_reset=True)
main(m, ports=[ctr.o])
from nmigen import *
from nmigen.cli import main
class System:
def __init__(self):
self.adr = Signal(16)
self.dat_r = Signal(8)
self.dat_w = Signal(8)
self.we = Signal()
def elaborate(self, platform):
m = Module()
m.submodules.cpu = Instance(
"CPU",
p_RESET_ADDR=0xfff0,
i_d_adr=self.adr,
i_d_dat_r=self.dat_r,
o_d_dat_w=self.dat_w,
i_d_we=self.we,
)
return m
if __name__ == "__main__":
sys = System()
main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we])
m.d.comb += self.o.eq(1)
with m.Else():
m.d.comb += self.o.eq(0)
m.d.sync += self.counter.eq(self.counter + 1)
# ramp up and down
m.d.sync += self.stretcher.eq(self.stretcher + 1)
with m.If(self.stretcher == self.stretch):
m.d.sync += self.stretcher.eq(0)
with m.If(self.updown == 1):
m.d.sync += self.value.eq(self.value + 1)
with m.If(self.value == 2**self.width - 2):
m.d.sync += self.updown.eq(0)
m.d.sync += [self.top.eq(1), self.bottom.eq(0)]
with m.If(self.updown == 0):
m.d.sync += self.value.eq(self.value - 1)
with m.If(self.value == 1):
m.d.sync += self.updown.eq(1)
m.d.sync += [self.top.eq(0), self.bottom.eq(1)]
with m.Else():
m.d.comb += self.o.eq(0)
return m
if __name__ == "__main__":
b = Breathe(width=5, stretch=5)
pins = (b.counter, b.value, b.enable, b.o, b.updown, b.top, b.bottom)
main(b, pins, name="top")
from nmigen import *
from nmigen.cli import main, pysim
class Counter:
def __init__(self, width):
self.v = Signal(width, reset=2**width-1)
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m
ctr = Counter(width=16)
if __name__ == "__main__":
main(ctr, ports=[ctr.o])
class ALU(Elaboratable):
def __init__(self, width):
self.op = Signal()
self.a = Signal(width)
self.b = Signal(width)
self.o = Signal(width)
self.add = Adder(width)
self.sub = Subtractor(width)
def elaborate(self, platform):
m = Module()
m.submodules.add = self.add
m.submodules.sub = self.sub
m.d.comb += [
self.add.a.eq(self.a),
self.sub.a.eq(self.a),
self.add.b.eq(self.b),
self.sub.b.eq(self.b),
]
with m.If(self.op):
m.d.comb += self.o.eq(self.sub.o)
with m.Else():
m.d.comb += self.o.eq(self.add.o)
return m
if __name__ == "__main__":
alu = ALU(width=16)
main(alu, ports=[alu.op, alu.a, alu.b, alu.o])
self.addr_w = addr_w
self.id_w = id_w
self.domain = domain
self.axilite = AxiLiteMaster(data_w, addr_w, name='M_AXI')
self.axi = AxiSlave(data_w, addr_w, id_w, user_w=0, name='S_AXI')
def elaborate(self, platform):
m = Module()
m.submodules.axi2axil_i = Instance(
'axi2axilite',
p_C_AXI_ID_WIDTH=self.id_w,
p_C_AXI_DATA_WIDTH=self.data_w,
p_C_AXI_ADDR_WIDTH=self.addr_w,
i_S_AXI_ACLK=ClockSignal(self.domain),
i_S_AXI_ARESETN=~ResetSignal(self.domain),
**get_ports_for_instance(self.axi, prefix='S_AXI_'),
**get_ports_for_instance(self.axilite, prefix='M_AXI_'),
)
if isinstance(platform, Platform):
for d in self.DEPENDENCIES:
add_verilog_file(platform, d)
return m
if __name__ == '__main__':
from nmigen.cli import main
core = Axi2AxiLite(32, 8, 5)
ports = [v for v in core.axi.fields.values()]
ports += [v for v in core.axilite.fields.values()]
main(core, None, ports=ports)
m.d.comb += [self.db.eq(cmds[idx]), self.rs.eq(rss[idx])]
wait_counter = Signal(10)
with m.FSM(reset='SETUP') as fsm:
with m.State('SETUP'):
m.d.comb += self.e.eq(0)
m.next = 'HOLD'
with m.State('HOLD'):
m.d.comb += self.e.eq(1)
m.d.sync += wait_counter.eq(0)
m.next = 'WAIT'
with m.State('WAIT'):
m.d.comb += self.e.eq(0)
m.d.sync += wait_counter.eq(wait_counter + 1)
with m.If(wait_counter == 20):
m.d.sync += idx.eq(idx + 1)
with m.If(idx == len(data) - 1):
m.next = 'DONE'
with m.Else():
m.next = 'SETUP'
return m.lower(platform)
if __name__ == '__main__':
lcd = LCD()
main(lcd, name='lcd', ports=[lcd.db, lcd.rs, lcd.e])
with m.If(~shift_counter.is_triggered()):
m.d.sync += dividend.eq(
Mux(quotient == 1, remainder, rot_dividend))
m.d.sync += self.o_digit_rd.eq(0)
with m.Else():
# digit complete
m.d.sync += dividend.eq(0)
m.d.sync += self.o_digit.eq(dividend)
m.d.sync += self.o_digit_rd.eq(1)
with m.Else():
# conversion complete
m.d.sync += self.o_digit.eq(dividend)
m.d.sync += self.o_digit_rd.eq(
~self.o_conv_rd) # 1-cycle digit strobe
m.d.sync += self.o_conv_rd.eq(1)
return m
def ports(self) -> List[Signal]:
return [
self.i_bin, self.i_bin_stb, self.o_digit, self.o_digit_rd,
self.o_conv_rd
]
if __name__ == '__main__':
bin2dec = Bin2Dec(8)
main(bin2dec, ports=[bin2dec.ports()])
# This loop will initiate number of SingleEncoder-s for every pixel.
for pixel, val_in, enc_out, enc_ctr, ssss, read_port in zip(
self.pixels, self.vals_in, self.encs_out, self.encs_ctr,
self.ssssx, self.read_ports):
m.d.comb += [
pixel.val_in.eq(val_in),
pixel.end_in.eq(self.end_in),
pixel.valid_in.eq(self.valid_in),
pixel.ssss.eq(ssss),
read_port.addr.eq(pixel.rp_addr),
pixel.rp_data.eq(read_port.data),
enc_out.eq(pixel.enc_out),
enc_ctr.eq(pixel.enc_ctr),
]
#if valid data
m.d.comb += self.valid_out.eq(self.pixels[0].valid_out)
m.d.comb += self.end_out.eq(self.pixels[0].end_out)
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 1,
"support_axi_lite": False,
}
e = Encode(config, constraints.Constraints())
main(e, ports=e.ios)
with m.State("DATA"):
with m.If(stb):
m.d.sync += [
bit.eq(bit - 1),
self.data.eq(Cat(self.i, self.data))
]
with m.If(bit == 0):
m.next = "STOP"
with m.State("STOP"):
with m.If(stb):
with m.If(self.i):
m.next = "DONE"
with m.Else():
m.next = "ERROR"
with m.State("DONE"):
m.d.comb += self.rdy.eq(1)
with m.If(self.ack):
m.next = "START"
m.d.comb += self.err.eq(fsm.ongoing("ERROR"))
with m.State("ERROR"):
pass
return m
if __name__ == "__main__":
rx = UARTReceiver(20)
main(rx, ports=[rx.i, rx.data, rx.rdy, rx.ack, rx.err])
from nmigen import *
from nmigen.cli import main
class ParMux:
def __init__(self, width):
self.s = Signal(3)
self.a = Signal(width)
self.b = Signal(width)
self.c = Signal(width)
self.o = Signal(width)
def elaborate(self, platform):
m = Module()
with m.Switch(self.s):
with m.Case("--1"):
m.d.comb += self.o.eq(self.a)
with m.Case("-1-"):
m.d.comb += self.o.eq(self.b)
with m.Case("1--"):
m.d.comb += self.o.eq(self.c)
with m.Case():
m.d.comb += self.o.eq(0)
return m
if __name__ == "__main__":
pmux = ParMux(width=16)
main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o])
p_DIVR=self.coeff.divr,
p_DIVF=self.coeff.divf,
p_DIVQ=self.coeff.divq,
p_FILTER_RANGE=0b001,
i_PACKAGEPIN=self.clk_pin,
i_RESETB=Const(1),
i_BYPASS=Const(0),
o_PLLOUTGLOBAL=ClockSignal(self.domain_name),
o_LOCK=pll_lock)
m = Module()
rst_signal = Signal()
if (self.external_rst is not None):
m.d.comb += rst_signal.eq(~pll_lock & self.external_rst)
else:
m.d.comb += rst_signal.eq(~pll_lock)
#rs = ResetSynchronizer(~pll_lock, domain=self.domain_name)
rs = ResetSynchronizer(rst_signal, domain=self.domain_name)
m.submodules += [pll, rs]
return m
# There is no point in simulating this, but you can generate Verilog.
if __name__ == '__main__':
pll = PLL(12, 30)
main(pll, ports=pll.ports)
from nmigen import *
from nmigen.cli import main, pysim
class Counter(Elaboratable):
def __init__(self, width):
self.v = Signal(width, reset=2**width-1)
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m
ctr = Counter(width=16)
if __name__ == "__main__":
main(ctr, ports=[ctr.o])
assert 0b110000000100 == (yield m.enc_out)
assert 12 == (yield m.enc_out_ctr)
yield
#validate test 3
assert 1 == (yield m.valid_out)
assert 0b1011001101101111000101010101011000011111010110101011111111010010101010101010101010110101010100000111100010010110101010101010 == (
yield m.enc_out)
assert 124 == (yield m.enc_out_ctr)
yield
assert 0 == (yield m.valid_out)
print("merge_test_1: succeeded.")
sim.add_clock(1e-8)
sim.add_sync_process(testbench())
sim.run()
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 4,
}
m = Merge(config, constraints.Constraints())
merge_test_1(m)
main(m, ports=m.ios)
for pixel, val_in, val_out, ssss, val_in_mns in zip(
self.pixels, self.vals_in, self.vals_out, self.ssssx,
self.vals_in_mns):
m.d.comb += [
pixel.val_in.eq(val_in),
pixel.valid.eq(self.valid_in),
pixel.end_in.eq(self.end_in),
pixel.val_in_mns.eq(val_in_mns),
]
m.d.comb += [
ssss.eq(pixel.ssss),
val_out.eq(pixel.val_out),
]
#if valid data
m.d.comb += self.valid_out.eq(self.pixels[0].valid_o)
# end
m.d.comb += self.end_out.eq(self.pixels[0].end_out)
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 1,
}
n = Normalize(config, constraints.Constraints())
main(n, ports=n.ios)
from types import SimpleNamespace
from nmigen import *
from nmigen.cli import main
class GPIO:
def __init__(self, pins, bus):
self.pins = pins
self.bus = bus
def elaborate(self, platform):
m = Module()
m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr])
with m.If(self.bus.we):
m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data)
return m
if __name__ == "__main__":
bus = Record([
("addr", 3),
("r_data", 1),
("w_data", 1),
("we", 1),
])
pins = Signal(8)
gpio = GPIO(Array(pins), bus)
main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we])
res = Signal(input_width)
for func in stages:
res = func(res)
self.widths.append(len(res))
self.input = AxiStream(self.widths[0], Direction.FANIN, name='input')
self.output = AxiStream(self.widths[-2], Direction.FANOUT, name='output')
def elaborate(self, platform):
m = Module()
comb = m.d.comb
modules = [PipelineStage(width, stage)
for width, stage in zip(self.widths[:-1], self.stages)]
for i, stage in enumerate(modules):
m.submodules['stage_' + str(i)] = stage
for i in range(1,len(modules)):
comb += modules[i].input.connect(modules[i-1].output)
comb += modules[0].input.connect(self.input)
comb += modules[-1].output.connect(self.output)
return m
if __name__ == "__main__":
stages = [lambda x: (x + x)[0:10],
lambda x: (x + (x << 1))[0:10],
lambda x: (x + (x >> 2))[0:10],
lambda x: (x + x)[0:10],
lambda x: x[0:5] + x[5::]]
pipeline = Pipeline(10, stages)
ports = [pipeline.input[f] for f in pipeline.input.fields]
ports += [pipeline.output[f] for f in pipeline.output.fields]
main(pipeline, ports=ports, name='pipeline')
#!/usr/bin/env python3
from types import SimpleNamespace
from nmigen import *
from nmigen.cli import main
class GPIO(Elaboratable):
def __init__(self, pins, bus):
self.pins = pins
self.bus = bus
def elaborate(self, platform):
m = Module()
m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr])
with m.If(self.bus.we):
m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data)
return m
if __name__ == "__main__":
bus = Record([
("addr", 3),
("r_data", 1),
("w_data", 1),
("we", 1),
])
pins = Signal(8)
gpio = GPIO(Array(pins), bus)
main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we])
from nmigen import *
from nmigen.cli import main
i, o = Signal(name="i"), Signal(name="o")
m = Module()
m.submodules += MultiReg(i, o)
if __name__ == "__main__":
main(m, ports=[i, o])
