def formal(dut_mod, **kw_args): parser = main_parser() args = parser.parse_args() m = Module() m.submodules.dut = dut = dut_mod(**kw_args, FORMAL=True) main_runner(parser, args, m, ports=dut.bus().ports())
def main(self): m = Module() ports = [] ports += self.verify_rtype(m) ports += self.verify_itype(m) ports += self.verify_stype(m) ports += self.verify_btype(m) ports += self.verify_utype(m) ports += self.verify_jtype(m) parser = main_parser() args = parser.parse_args() main_runner(parser, args, m, ports=ports)
def main(): # parser: add options parser = argparse.ArgumentParser() # add (extra) arguments parser.add_argument("--config-file", type=str, help="configuration file", required=True) cli.main_parser(parser) args = parser.parse_args() # load the configuration file configuration = cfg.Configuration(args.config_file) # create the CPU cpu = Bellatrix(configuration) ports = [ # instruction port cpu.iport.addr, cpu.iport.dat_w, cpu.iport.sel, cpu.iport.we, cpu.iport.cyc, cpu.iport.stb, cpu.iport.cti, cpu.iport.bte, cpu.iport.dat_r, cpu.iport.ack, cpu.iport.err, # data port cpu.dport.addr, cpu.dport.dat_w, cpu.dport.sel, cpu.dport.we, cpu.dport.cyc, cpu.dport.stb, cpu.dport.cti, cpu.dport.bte, cpu.dport.dat_r, cpu.dport.ack, cpu.dport.err, # exceptions cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt ] # run cli.main_runner(parser, args, cpu, name='bellatrix_core', ports=ports)
def main(): m = Module() clock = ClockInfo("i") m.domains.i = clock.domain m.submodules.core = core = Core(clock) core.aux_ports.append(clock.clk) core.aux_ports.append(clock.rst) parser = main_parser() parser.add_argument("--proof", type=str, help="generate signle proof") args = parser.parse_args() required_proof = args.proof # RV32I core.add_instruction(OpImmInstr()) core.add_instruction(JalrInstr()) core.add_instruction(JalInstr()) core.add_instruction(LuiInstr()) core.add_instruction(AuipcInstr()) core.add_instruction(BeqBneInstr()) core.add_instruction(BltBgeInstr()) core.add_instruction(BltuBgeuInstr()) core.add_instruction(LbLbuInstr()) core.add_instruction(LhLhuInstr()) core.add_instruction(LwInstr()) proof_instance = None generate_proof = "generate" in sys.argv all_proofs = [ proof for instruction in core.instructions for proof in instruction.proofs() ] if required_proof: for proof_class in all_proofs: proof_name = proof_class.__name__.lower() if proof_name.startswith("proof"): proof_name = proof_name[len("proof"):] if required_proof == "ALL" or proof_name == required_proof: proof_instance = proof_class() if generate_proof: proof_instance.run(m, core) if required_proof is not None and not proof_instance: raise Exception(f"Unknown proof {required_proof}") if "generate" in sys.argv: main_runner(parser, args, m, ports=core.ports()) else: assert proof_instance, "use --proof proof to run simulation from proof/instruction" core.simulate(m, clock, proof_instance.simulate())
return m # Formal Verification if __name__ == "__main__": parser = main_parser() args = parser.parse_args() m = Module() i_ce = Signal(1, reset=1) i_data = Signal(1, reset=0) o_data = Signal(1) m.submodules.dblpipe = dblpipe = DblPipe(i_ce, i_data, o_data, \ fv_mode = True) main_runner(parser, args, m, ports = dblpipe.ports()) # Simulation # if __name__ == "__main__": # m = Module() # i_ce = Signal(1, reset=1) # i_data = Signal(1, reset=0) # o_data = Signal(1) # m.submodules.dblpipe = dblpipe = DblPipe(i_ce, i_data, o_data) # sim = Simulator(m) # def process(): # for i in range(1000): # yield
cli.main_parser(parser) args = parser.parse_args() tx = Signal() rx = Signal(reset=1) if args.type == "sim": freq = 4800 tb = UART(tx, rx, clk_freq=freq, baud_rate=1200) with pysim.Simulator( tb, vcd_file=open("ctrl.vcd", "w"), gtkw_file=open("ctrl.gtkw", "w"), traces=[tx, rx], ) as sim: sim.add_clock(freq) sim.add_sync_process(_test(tx, rx, tb)) # sim.run_until(100e-6, run_passive=True) sim.run() if args.type == "uart": tb = UART(tx, rx, clk_freq=4800, baud_rate=1200) ios = (tx, rx, tb.TX.tx_data, tb.RX.rx_data) cli.main_runner(parser, args, tb, name=args.type, ports=ios) if args.type == "loopback": tb = Loopback(tx, rx) ios = (tx, rx) cli.main_runner(parser, args, tb, name=args.type, ports=ios)
if __name__ == "__main__": import argparse from nmigen import cli parser = argparse.ArgumentParser() cli.main_parser(parser) args = parser.parse_args() platform = TinyFPGABXPlatform() tb = EL(platform) ios = () cli.main_runner(parser, args, tb,platform=platform,ports=ios) # python sim_fail.py simulate -c 1000 -v test.vcd #Traceback (most recent call last): # File "sim_fail.py", line 36, in <module> # cli.main_runner(parser, args, tb,platform=platform,ports=ios) # File "/usr/local/lib/python3.6/dist-packages/nmigen/cli.py", line 71, in main_runner # sim.run_until(args.sync_period * args.sync_clocks, run_passive=True) # File "/usr/local/lib/python3.6/dist-packages/nmigen/back/pysim.py", line 802, in run_until # if not self.step(run_passive): # File "/usr/local/lib/python3.6/dist-packages/nmigen/back/pysim.py", line 786, in step # self._run_process(process) # File "/usr/local/lib/python3.6/dist-packages/nmigen/back/pysim.py", line 749, in _run_process # process.throw(e) # File "/usr/local/lib/python3.6/dist-packages/nmigen/back/pysim.py", line 442, in clk_process # yield clk.eq(1)
args = parser.parse_args() if args.type == "alu": tb = _ALU(16) ios = (tb.s_a, tb.s_b, tb.s_o, tb.c_sel) if args.type == "sru": tb = _SRU(16) ios = (tb.s_i, tb.s_c, tb.r_o, tb.c_ld, tb.c_dir) if args.type == "bus": tb = BonelessFSMTestbench() ios = (tb.ext_port.adr, tb.ext_port.re, tb.ext_port.dat_r, tb.ext_port.we, tb.ext_port.dat_w) if args.type == "pins": tb = BonelessFSMTestbench(has_pins=True) ios = (tb.pins,) if args.type == "formal": tb = BonelessFSMFormal() ios = tb.core.formal._all + [ tb.mem_rdport.adr, tb.mem_rdport.dat_r, tb.mem_rdport.re, tb.mem_wrport.adr, tb.mem_wrport.dat_w, tb.mem_wrport.we, tb.ext_port.adr, tb.ext_port.dat_r, tb.ext_port.re, tb.ext_port.dat_w, tb.ext_port.we, ] cli.main_runner(parser, args, tb.get_fragment(), name="boneless", ports=ios)
m.d.comb += Assert(~self.i_busy) m.d.comb += Assert(self.o_a_busy) m.d.comb += Assert(self.o_req == self.i_b_req) m.d.comb += Assert(self.o_data == self.i_b_data) return m # Formal Verification if __name__ == "__main__": parser = main_parser() args = parser.parse_args() m = Module() i_reset = Signal(1, reset=0) i_a_req = Signal(1, reset=0) i_a_data = Signal(1, reset=0) o_a_busy = Signal(1) i_b_req = Signal(1, reset=0) i_b_data = Signal(1, reset=0) o_b_busy = Signal(1) o_req = Signal(1) o_data = Signal(1) i_busy = Signal(1, reset=0) m.submodules.reqarb = reqarb = ReqArb(i_reset, \ i_a_req, i_a_data, o_a_busy, \ i_b_req, i_b_data, o_b_busy, \ o_req, o_data, i_busy, fv_mode = True) main_runner(parser, args, m, ports=reqarb.ports())
valid = Signal() m.d.sync += ready.eq(self.uir) m.d.sync += self.uid.eq(0) m.d.sync += self.uiv.eq(0) m.d.sync += self.leds[1].eq(valid) m.d.sync += self.leds[0].eq(self.uir) m.d.sync += self.leds[2].eq(0) m.d.sync += self.leds[3].eq(ready) m.d.comb += data.eq(self.uod) m.d.comb += valid.eq(self.uov) m.d.sync += self.uor.eq(1) return m if __name__ == "__main__": import argparse from nmigen import cli parser = argparse.ArgumentParser() cli.main_parser(parser) args = parser.parse_args() tb= Loopback() ios = (tb.uid,tb.uod,tb.uiv,tb.uir,tb.uov,tb.uor,tb.leds) cli.main_runner(parser,args,tb,name="loopback",ports=ios)
from nmigen import Elaboratable, Module, Signal, Array, unsigned, Const from nmigen.build import Platform from nmigen.cli import main_parser, main_runner from src.ldpc_decoder import LDPC_Decoder if __name__ == "__main__": #Instantiate a command line argument parser parser = main_parser() args = parser.parse_args() #Instantiate an nMigen Module m = Module() #Instantiate the Parity Check Matrix 'H' for generating ldpc Code Words #https://en.wikipedia.org/wiki/Low-density_parity-check_code parityCheckMatrix = [[0b111100], [0b001101], [0b100110]] #Instantiate the LDPC_Decoder Module with the parity check matrix, input codeword size and output data size as parameters m.submodules.LDPC_Decoder = LDPC_Decoder = LDPC_Decoder( parityCheckMatrix, 6, 3) main_runner(parser, args, m, ports=[ LDPC_Decoder.data_input, LDPC_Decoder.data_output, LDPC_Decoder.start, LDPC_Decoder.done, LDPC_Decoder.success ])
if __name__ == "__main__": parser = main_parser() parser.add_argument("--oper") args = parser.parse_args() oper: Optional[Operation] = None if args.oper is not None: oper = Operation[args.oper] m = Module() m.submodules.alu = alu = ALU_big(oper) if oper is not None: m.d.comb += Assume(~ResetSignal()) m.d.comb += Assume(alu.oper == oper) main_runner(parser, args, m, ports=alu.ports()) else: sim = Simulator(m) def process(): yield yield alu.inputa.eq(0x12) yield alu.inputb.eq(0x34) yield alu.oper.eq(Operation.ADC) yield yield yield alu.inputa.eq(0x7F) yield alu.inputb.eq(0x7F) yield alu.oper.eq(Operation.ADC) yield
with m.If(Initial()): m.d.sync += Assume(ResetSignal()) with m.Else(): m.d.sync += Assume(~ResetSignal()) # A time slot delayed because PC and addr need to sync with m.If(time == 2): m.d.sync += Assume(~core.snapshot.taken) with m.If(time == 3): m.d.sync += Cover(core.snapshot.taken) m.d.sync += Assume(core.snapshot.taken) m.d.sync += Cover(Fell(core.snapshot.taken)) main_runner( parser, args, m, ports=core.ports() + [ClockSignal(), ResetSignal()] ) else: # Fake memory mem = { 0x0000: 0x5F, 0x1000: 0x12, 0x2000: 0x34, 0x1234: 0x5F, 0x1334: 0x00, 0x1434: 0x00, } with m.Switch(core.addr): for addr, data in mem.items(): with m.Case(addr):
#Instantiate a command line argument parser parser = main_parser() args = parser.parse_args() #Instantiate an nMigen Module m = Module() #Instantiate the Generator Matrix 'G' for generating ldpc Code Words #https://en.wikipedia.org/wiki/Low-density_parity-check_code#Example_Encoder generatorMatrix = [ [0b100101], [0b010111], [0b001110], ] #Instantiate the LDPC_Encoder Module with the generator matrix and output codeword size as parameters m.submodules.LDPC_Encoder = LDPC_Encoder = LDPC_Encoder(generatorMatrix, 6) #Run the design verification verification_statements(m) main_runner(parser, args, m, ports=[ LDPC_Encoder.data_input, LDPC_Encoder.data_output, LDPC_Encoder.start, LDPC_Encoder.done ])
args = parser.parse_args() b2d = Bin2Dec(8) m = Module() m.submodules.b2d = b2d m.d.comb += Cover(b2d.o_digit_rd == 1) m.d.comb += Cover(b2d.o_conv_rd == 1) # o_digit_rd is a 1-cycle strobe with m.If((Past(b2d.o_digit_rd, 2) == 0) & (Past(b2d.o_digit_rd, 1) == 1)): m.d.comb += Assert(b2d.o_digit_rd == 0) # i_bin_stb resets all outputs with m.If(Past(b2d.i_bin_stb) == 1): m.d.comb += Assert(b2d.o_digit == 0) m.d.comb += Assert(b2d.o_digit_rd == 0) m.d.comb += Assert(b2d.o_conv_rd == 0) # o_digit is stable if o_digit_rd is low with m.If((Past(ResetSignal()) == 0) & (Past(b2d.i_bin_stb) == 0) & (b2d.o_digit_rd == 0)): m.d.comb += Assert(Stable(b2d.o_digit)) # o_digit_rd rises with o_conv_rd and falls on the next cycle with m.If(Rose(b2d.o_conv_rd, 2)): m.d.comb += Assert(Rose(b2d.o_digit_rd, 2)) m.d.comb += Assert(Fell(b2d.o_digit_rd, 1)) main_runner(parser, args, m, ports=b2d.ports())
def setup(validator: Optional[Base]): result = CliSetup( Module(), Core(validator), ClockDomain("ph1"), ClockSignal("ph1"), ) result.m.submodules.core = result.core result.m.domains.ph1 = result.ph1 result.ph1.rst = result.core.Rst return result if __name__ == "__main__": parser = main_parser() parser.add_argument("--validator") args = parser.parse_args() verification: Optional[Base] = None if args.validator is not None: module = importlib.import_module(f"Validators.{args.validator}") formal_class = getattr(module, f"{args.validator}") verification = formal_class() s = setup(verification) main_runner(parser, args, s.m, ports=s.core.ports() + [s.ph1clk])
out_carry = alu._ccs[Flags.C] in1_dec = 10 * in1_hi + in1_lo in2_dec = 10 * in2_hi + in2_lo out_dec = 100 * out_carry + 10 * out_hi + out_lo m.d.ph1 += [ Assume(Past(alu.func) == ALU8Func.ADC), Assume(alu.func == ALU8Func.DAA), Assume(alu.input1 == Past(alu.output)), Assume(in1_lo < 10), Assume(in1_hi < 10), Assume(in2_lo < 10), Assume(in2_hi < 10), ] m.d.ph1 += [ Assert((in1_dec + in2_dec + in_carry) == out_dec), Assert(alu._ccs[Flags.N] == alu.output[7]), Assert(alu._ccs[Flags.Z] == (alu.output == 0)), ] m.d.ph1 += Cover(out_dec == 142) main_runner( parser, args, m, ports=alu.input_ports() + alu2.input_ports() + [ph1clk, rst, test_daa], )
# Formal Verification if __name__ == "__main__": parser = main_parser() args = parser.parse_args() m = Module() i_reset = Signal(1, reset=0) i_ce = Signal(1, reset=1) i_in = Signal(1, reset=0) o_bit = Signal(1) m.submodules.lfsr_fib = lfsr_fib = LFSRFib(i_reset, i_ce, i_in, \ o_bit, fv_mode = True) main_runner(parser, args, m, ports=lfsr_fib.ports()) # Simulation # if __name__ == "__main__": # m = Module() # i_reset = Signal(1, reset=0) # i_ce = Signal(1, reset=1) # i_in = Signal(1, reset=0) # o_bit = Signal(1) # m.submodules.lfsr_fib = lfsr_fib = LFSRFib(i_reset, i_ce, i_in, \ # o_bit) # sim = Simulator(m) # def process(): # for i in range(1000):
m.d.sync += self.counter.eq(MAX_AMOUNT - 1) with m.Elif(self.counter != 0): m.d.sync += self.counter.eq(self.counter - 1) m.d.sync += self.o_busy.eq((~self.i_reset) & \ ((self.i_start_signal & (self.counter == 0)) | \ (self.counter > 1))) if self.fv_mode: f_past_valid = Signal(1, reset=0) m.d.sync += f_past_valid.eq(1) m.d.comb += Assert(self.counter < MAX_AMOUNT) with m.If(f_past_valid & Past(self.i_start_signal) & Past(self.o_busy)): m.d.comb += Assume(self.i_start_signal) with m.Elif(f_past_valid & Past(self.i_start_signal) & ~Past(self.o_busy)): m.d.comb += Assume(~self.i_start_signal) m.d.comb += Assert(self.o_busy == (self.counter != 0)) with m.If(f_past_valid & Past(self.counter) != 0): m.d.comb += Assert(self.counter < Past(self.counter)) return m if __name__ == "__main__": parser = main_parser() args = parser.parse_args() m = Module() m.submodules.counter = counter = BusyCounter(True) main_runner(parser, args, m, ports=counter.ports())
# ------------------------------------------------------------------------------------------------- import argparse from nmigen import cli if __name__ == "__main__": parser = argparse.ArgumentParser() parser.add_argument("-t", "--type", choices=["4lut"], default="4lut") parser.add_argument("-w", "--width", type=int, default=16) cli.main_parser(parser) args = parser.parse_args() if args.type == "4lut": alsru = ALSRU_4LUT(args.width) ctrl = (alsru.ctrl.s, alsru.ctrl.x, alsru.ctrl.y, alsru.ctrl.o) ports = ( alsru.a, alsru.b, alsru.o, alsru.r, alsru.ci, alsru.co, alsru.vo, alsru.si, alsru.so, *ctrl, ) cli.main_runner(parser, args, alsru, name="alsru", ports=ports)
dut.c_width, dut.c_pcrel, ) if args.type == "instruction": dut = InstructionDecoder(alsru_cls=ALSRU_4LUT) ports = ( dut.i_pc, dut.i_insn, dut.o_imm16, dut.o_rsd, dut.o_ra, dut.o_rb, dut.o_cond, dut.o_flag, dut.o_shift, dut.o_multi, dut.o_xbus, dut.o_skip, dut.o_ld_a, dut.o_ld_b, dut.o_st_r, dut.o_st_w, dut.o_st_pc, dut.o_op, dut.o_ci, dut.o_si, ) cli.main_runner(parser, args, dut, ports=ports)
m.submodules.core = core = CoreFSM( alsru_cls=ALSRU_4LUT, # reset_pc=0, memory=self.memory, reset_w=self.memsize - 8, ) self.o_bus_addr = core.o_bus_addr self.o_ext_re = core.o_ext_re self.o_ext_we = core.o_ext_we self.o_ext_data = core.o_ext_data self.i_ext_data = core.i_ext_data self.insert_periph(m) return m if __name__ == "__main__": import argparse from nmigen import cli parser = argparse.ArgumentParser() cli.main_parser(parser) args = parser.parse_args() tb = Boneless() ios = () cli.main_runner(parser, args, tb, name="boneless_core", ports=ios)
def __main(): m = Module() xlen = 32 m.submodules.alu1 = alu1 = ALU(xlen, "A", include_invalid_op=True) m.submodules.alu2 = alu2 = ALU(xlen, "B") op = Signal(OpAlu) en = Signal() lhs = Signal(32) rhs = Signal(32) ports = [op, en, lhs, rhs] m.d.comb += alu1.op.eq(op) m.d.comb += alu2.op.eq(op) m.d.comb += alu1.en.eq(en) m.d.comb += alu2.en.eq(en) m.d.comb += alu1.lhs.eq(lhs) m.d.comb += alu1.rhs.eq(rhs) m.d.comb += alu2.lhs.eq(rhs) m.d.comb += alu2.rhs.eq(lhs) lhs_signed = as_signed(m, lhs) rhs_signed = as_signed(m, rhs) with m.If(alu1.en): with m.If(alu1.op == OpAlu.XOR): m.d.comb += Assert(alu1.invalid_op == 0) m.d.comb += Assert(alu1.output == alu2.output) m.d.comb += Assert(alu1.output == (lhs ^ rhs)) # NOT instruction with m.If(alu1.rhs == -1): m.d.comb += Assert(alu1.output == ~alu1.lhs) with m.Elif(alu1.op == OpAlu.ADD): m.d.comb += Assert(alu1.invalid_op == 0) m.d.comb += Assert(alu1.output == alu2.output) m.d.comb += Assert(alu1.output == (lhs + rhs)[:xlen]) # MV instruction with m.If(alu1.rhs == 0): m.d.comb += Assert(alu1.output == alu1.lhs) with m.Elif(alu1.op == OpAlu.SLT): m.d.comb += Assert(alu1.invalid_op == 0) with m.If(lhs_signed < rhs_signed): m.d.comb += Assert(alu1.output == 1) with m.Else(): m.d.comb += Assert(alu1.output == 0) with m.Elif(alu1.op == OpAlu.SLTU): m.d.comb += Assert(alu1.invalid_op == 0) m.d.comb += Assert(alu1.output == (lhs < rhs)) # Explicit mention of rhs = 1 with m.If(rhs == 1): with m.If(alu1.output == 1): m.d.comb += Assert(lhs == 0) with m.Elif(alu1.op == OpAlu.AND): m.d.comb += Assert(alu1.invalid_op == 0) m.d.comb += Assert(alu1.output == alu2.output) m.d.comb += Assert(alu1.output == (lhs & rhs)) with m.Elif(alu1.op == OpAlu.OR): m.d.comb += Assert(alu1.invalid_op == 0) m.d.comb += Assert(alu1.output == alu2.output) m.d.comb += Assert(alu1.output == (lhs | rhs)) with m.Else(): m.d.comb += Assert(alu1.invalid_op) with m.Else(): m.d.comb += Assert(alu1.output == 0) m.d.comb += Assert(alu2.output == 0) parser = main_parser() args = parser.parse_args() main_runner(parser, args, m, ports=ports + alu1.ports() + alu2.ports())
def main(*args, **kwargs): parser = cocotb_parser() parsed_args = parser.parse_args() main_runner(parser, parsed_args, *args, **kwargs) cocotb_runner(parser, parsed_args, *args, **kwargs)
sel = yield cpu.bus.sel_o if stb: if we: msk = 0xff if sel & 1 else 0 msk |= 0xff00 if sel & 2 else 0 msk |= 0xff0000 if sel & 4 else 0 msk |= 0xff000000 if sel & 8 else 0 mem[adr] = (mem.get(adr, 0) & ~msk) | ( (yield cpu.bus.dat_o) & msk) print("Mem write addr {:08x} = {:08x}".format( adr * 4, mem[adr])) else: if not adr in mem: do = 0x00213200 else: do = mem[adr] yield cpu.bus.dat_i.eq(do) yield sim = Simulator(top) sim.add_clock(1e-7) sim.add_sync_process(process) with sim.write_vcd("test.vcd", "test.gtkw", traces=cpu.ports()): sim.run() else: parser = main_parser() args = parser.parse_args() m1, ports1 = ALU.formal() m2, ports2 = Cpu(32, 16).formal() main_runner(parser, args, m2, ports=ports2)
output locked ); SB_PLL40_CORE #( .FEEDBACK_PATH("SIMPLE"), .DIVR(4'b0000), // DIVR = 0 .DIVF(7'b0101111), // DIVF = 47 .DIVQ(3'b100), // DIVQ = 4 .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 ) uut ( .LOCK(locked), .RESETB(1'b1), .BYPASS(1'b0), .REFERENCECLK(clock_in), .PLLOUTCORE(clock_out) ); """ if __name__ == "__main__": print("PLL") import argparse from nmigen import cli parser = argparse.ArgumentParser() cli.main_parser(parser) args = parser.parse_args() tb = pll() ios = () cli.main_runner(parser, args, tb, name="pll", ports=ios)
def main(): parser = argparse.ArgumentParser( formatter_class=argparse.ArgumentDefaultsHelpFormatter) parser.add_argument("--reset-addr", type=lambda s: int(s, 16), default="0x00000000", help="reset vector address") parser.add_argument("--with-icache", default=False, action="store_true", help="enable the instruction cache") parser.add_argument("--with-dcache", default=False, action="store_true", help="enable the data cache") parser.add_argument("--with-muldiv", default=False, action="store_true", help="enable RV32M support") parser.add_argument("--with-debug", default=False, action="store_true", help="enable the Debug Module") parser.add_argument("--with-trigger", default=False, action="store_true", help="enable the Trigger Module") parser.add_argument("--with-rvfi", default=False, action="store_true", help="enable the riscv-formal interface") icache_group = parser.add_argument_group("icache options") icache_group.add_argument("--icache-nways", type=int, choices=[1, 2], default=1, help="number of ways") icache_group.add_argument("--icache-nlines", type=int, default=32, help="number of lines") icache_group.add_argument("--icache-nwords", type=int, choices=[4, 8, 16], default=4, help="number of words in a line") icache_group.add_argument("--icache-base", type=lambda s: int(s, 16), default="0x00000000", help="base address") icache_group.add_argument("--icache-limit", type=lambda s: int(s, 16), default="0x80000000", help="limit address") dcache_group = parser.add_argument_group("dcache options") dcache_group.add_argument("--dcache-nways", type=int, choices=[1, 2], default=1, help="number of ways") dcache_group.add_argument("--dcache-nlines", type=int, default=32, help="number of lines") dcache_group.add_argument("--dcache-nwords", type=int, choices=[4, 8, 16], default=4, help="number of words in a line") dcache_group.add_argument("--dcache-base", type=lambda s: int(s, 16), default="0x00000000", help="base address") dcache_group.add_argument("--dcache-limit", type=lambda s: int(s, 16), default="0x80000000", help="limit address") trigger_group = parser.add_argument_group("trigger options") trigger_group.add_argument("--nb-triggers", type=int, default=8, help="number of triggers") cli.main_parser(parser) args = parser.parse_args() if args.with_debug and not args.with_trigger: warnings.warn( "Support for hardware breakpoints requires --with-trigger") cpu = Minerva(args.reset_addr, args.with_icache, args.icache_nways, args.icache_nlines, args.icache_nwords, args.icache_base, args.icache_limit, args.with_dcache, args.dcache_nways, args.dcache_nlines, args.dcache_nwords, args.dcache_base, args.dcache_limit, args.with_muldiv, args.with_debug, args.with_trigger, args.nb_triggers, args.with_rvfi) ports = [ cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt, cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc, cpu.ibus.dat_r, cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb, cpu.ibus.we, cpu.ibus.err, cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte, cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r, cpu.dbus.dat_w, cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err ] if args.with_debug: ports += [cpu.jtag.tck, cpu.jtag.tdi, cpu.jtag.tdo, cpu.jtag.tms] if args.with_rvfi: ports += [ cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap, cpu.rvfi.halt, cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl, cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr, cpu.rvfi.rs1_rdata, cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata, cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr, cpu.rvfi.mem_rmask, cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata, cpu.rvfi.mem_wdata ] cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
with m.If(cycle2 == 20): m.d.ph1 += Cover(core.formalData.snapshot_taken & core.end_instr_flag) m.d.ph1 += Assume(core.formalData.snapshot_taken & core.end_instr_flag) # Verify reset does what it's supposed to with m.If(Past(rst, 4) & ~Past(rst, 3) & ~Past(rst, 2) & ~Past(rst)): m.d.ph1 += Assert(Past(core.Addr, 2) == 0xFFFE) m.d.ph1 += Assert(Past(core.Addr) == 0xFFFF) m.d.ph1 += Assert(core.Addr[8:] == Past(core.Din, 2)) m.d.ph1 += Assert(core.Addr[:8] == Past(core.Din)) m.d.ph1 += Assert(core.Addr == core.pc) main_runner(parser, args, m, ports=core.ports() + [ph1clk, rst]) else: # Fake memory mem = { 0xFFFE: 0x12, 0xFFFF: 0x34, 0x1234: 0x7E, # JMP 0xA010 0x1235: 0xA0, 0x1236: 0x10, 0xA010: 0x01, # NOP } with m.Switch(core.Addr): for addr, data in mem.items(): with m.Case(addr): m.d.comb += core.Din.eq(data)
Assert(alu._ccs[_H] == h), Assert(alu._ccs[_N] == n), Assert(alu._ccs[_Z] == z), Assert(alu._ccs[_V] == v), Assert(alu._ccs[_C] == c), Assert(alu._ccs[_I] == alu.ccs[_I]), ] with m.Case(ALU8Func.SUB, ALU8Func.SBC): with m.If(alu.func == ALU8Func.SUB): m.d.comb += carry_in.eq(0) with m.Else(): m.d.comb += carry_in.eq(alu.ccs[_C]) n = sum9[7] c = ~sum9[8] z = (sum9[:8] == 0) v = (sum8[7] ^ sum9[8]) m.d.comb += [ sum9.eq(alu.input1 + ~alu.input2 + ~carry_in), sum8.eq(alu.input1[:7] + ~alu.input2[:7] + ~carry_in), Assert(sum9[:8] == (alu.input1 - alu.input2 - carry_in)[:8]), Assert(alu.output == sum9[:8]), Assert(alu._ccs[_N] == n), Assert(alu._ccs[_Z] == z), Assert(alu._ccs[_V] == v), Assert(alu._ccs[_C] == c), Assert(alu._ccs[_H] == alu.ccs[_H]), Assert(alu._ccs[_I] == alu.ccs[_I]), ] main_runner(parser, args, m, ports=alu.input_ports() + [ph1clk, rst])