def __init__(self, *, divisor, divisor_bits=None, data_bits=8, pins=None):
self.divisor = Signal(divisor_bits or bits_for(divisor), reset=divisor)
self.data = Signal(data_bits)
self.rdy = Signal()
self.ack = Signal()
self.o = Signal()
self._pins = pins
def __init__(self, *, divisor, divisor_bits=None, data_bits=8, pins=None, depth=0):
self.divisor = Signal(divisor_bits or bits_for(divisor), reset=divisor)
self.data = Signal(data_bits)
self.err = Record([("overflow", 1), ("frame", 1)])
self.rdy = Signal()
self.ack = Signal()
self.i = Signal()
self._pins = pins
self.depth = depth
def write_port(self):
port = Record([("addr", bits_for(self.depth)), ("en", 1), ("data", self.width)])
self._write_ports.append(port)
return port
def __init__(self, *, divisor, divisor_bits=None, **kwargs):
self.divisor = Signal(divisor_bits or bits_for(divisor), reset=divisor)
self.rx = AsyncSerialRX(**kwargs)
self.tx = AsyncSerialTX(**kwargs)