def formal(cls) -> Tuple[Module, List[Signal]]:
m = Module()
ph = ClockDomain("ph")
clk = ClockSignal("ph")
m.domains += ph
m.d.sync += clk.eq(~clk)
s = IC_7416374(clk="ph")
m.submodules += s
with m.If(s.n_oe):
m.d.comb += Assert(s.q == 0)
with m.If(~s.n_oe & Rose(clk)):
m.d.comb += Assert(s.q == Past(s.d))
with m.If(~s.n_oe & Fell(clk) & ~Past(s.n_oe)):
m.d.comb += Assert(s.q == Past(s.q))
sync_clk = ClockSignal("sync")
sync_rst = ResetSignal("sync")
# Make sure the clock is clocking
m.d.comb += Assume(sync_clk == ~Past(sync_clk))
# Don't want to test what happens when we reset.
m.d.comb += Assume(~sync_rst)
m.d.comb += Assume(~ResetSignal("ph"))
return m, [sync_clk, sync_rst, s.n_oe, s.q, s.d]
def formal(cls) -> Tuple[Module, List[Signal]]:
m = Module()
ph = ClockDomain("ph")
clk = ClockSignal("ph")
m.domains += ph
m.d.sync += clk.eq(~clk)
s = IC_reg32_with_mux(clk="ph", N=2, faster=True)
m.submodules += s
sync_clk = ClockSignal("sync")
sync_rst = ResetSignal("sync")
with m.If(Rose(clk)):
with m.Switch(~Past(s.n_sel)):
with m.Case(0b11):
m.d.comb += Assert(0)
with m.Case(0b01):
m.d.comb += Assert(s.q == Past(s.d[0]))
with m.Case(0b10):
m.d.comb += Assert(s.q == Past(s.d[1]))
with m.Default():
m.d.comb += Assert(s.q == Past(s.q))
# Make sure the clock is clocking
m.d.comb += Assume(sync_clk == ~Past(sync_clk))
# Don't want to test what happens when we reset.
m.d.comb += Assume(~sync_rst)
m.d.comb += Assume(~ResetSignal("ph"))
m.d.comb += Assume(s.n_sel != 0)
return m, [sync_clk, sync_rst, s.d[0], s.d[1], s.n_sel, s.q]
def elaborate(self, platform: Platform) -> Module:
m = Module()
m.domains.ramg = ClockDomain(async_reset=True, local=True)
m.domains.romb0 = ClockDomain(async_reset=True, local=True)
m.domains.romb1 = ClockDomain(async_reset=True, local=True)
m.domains.ramb = ClockDomain(async_reset=True, local=True)
ramg_clk = ClockSignal("ramg")
romb0_clk = ClockSignal("romb0")
romb1_clk = ClockSignal("romb1")
ramb_clk = ClockSignal("ramb")
m.d.comb += [
ResetSignal("ramg").eq(self.cart_rst),
ResetSignal("romb0").eq(self.cart_rst),
ResetSignal("romb1").eq(self.cart_rst),
ResetSignal("ramb").eq(self.cart_rst),
]
ramg = Signal(8)
romb0 = Signal(8, reset=0x01)
romb1 = Signal(1)
ramb = Signal(4)
m.d.ramg += ramg.eq(self.cart_data)
m.d.romb0 += romb0.eq(self.cart_data)
m.d.romb1 += romb1.eq(self.cart_data)
m.d.ramb += ramb.eq(self.cart_data)
m.d.comb += [
ramg_clk.eq(1),
romb0_clk.eq(1),
romb1_clk.eq(1),
ramb_clk.eq(1)
]
with m.If(self.cart_wr):
with m.Switch(self.cart_addr[12:]):
with m.Case(0b0000):
m.d.comb += ramg_clk.eq(0)
with m.Case(0b0001):
m.d.comb += ramg_clk.eq(0)
with m.Case(0b0010):
m.d.comb += romb0_clk.eq(0)
with m.Case(0b0011):
m.d.comb += romb1_clk.eq(0)
with m.Case(0b0100):
m.d.comb += ramb_clk.eq(0)
with m.Case(0b0101):
m.d.comb += ramb_clk.eq(0)
m.d.comb += [
self.ram_en.eq(ramg == 0x0A),
self.ram_bank.eq(ramb),
]
with m.If(self.cart_addr[14]):
m.d.comb += self.rom_bank.eq(Cat(romb0, romb1))
with m.Else():
m.d.comb += self.rom_bank.eq(0)
return m