def elaborate(self, platform: Platform) -> Module:
m = Module()
m.d.sync += self.PSW.eq(self._psw)
m.d.comb += self._psw.eq(self.PSW)
with m.Switch(self.oper):
with m.Case(Operation.NOP):
if self.verification is Operation.NOP:
with m.If(~Initial()):
m.d.comb += [
Assert(self._psw.N == self.PSW.N),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == self.PSW.Z),
Assert(self._psw.C == self.PSW.C),
]
with m.Case(Operation.ADC):
low = Cat(self.result[:4], self._psw.H)
high = Cat(self.result[4:], self._psw.C)
m.d.comb += [
low.eq(self.inputa[:4] + self.inputb[:4] + self.PSW.C),
high.eq(self.inputa[4:] + self.inputb[4:] + self._psw.H),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
self._psw.V.eq(self.result[7] != self._psw.C),
]
if self.verification is Operation.ADC:
r = Signal(8)
f = Signal(9)
h = Signal(5)
m.d.comb += [
r.eq(self.inputa.as_signed() +
self.inputb.as_signed() + self.PSW.C),
f.eq(self.inputa + self.inputb + self.PSW.C),
h.eq(self.inputa[:4] + self.inputb[:4] + self.PSW.C),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self.result == f[:8]),
Assert(self._psw.N == f[7]),
Assert(self._psw.V == (f[7] ^ f[8])),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == h[4]),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(f[:8].bool())),
Assert(self._psw.C == f[8]),
]
with m.Case(Operation.SBC):
low = Cat(self.result[:4], self._psw.H)
high = Cat(self.result[4:], self._psw.C)
m.d.comb += [
low.eq(self.inputa[:4] - self.inputb[:4] - self.PSW.C),
high.eq(self.inputa[4:] - self.inputb[4:] - self._psw.H),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
self._psw.V.eq(self.result[7] != self._psw.C),
]
if self.verification is Operation.SBC:
r = Signal(8)
f = Signal(9)
h = Signal(5)
m.d.comb += [
r.eq(self.inputa.as_signed() -
self.inputb.as_signed() - self.PSW.C),
f.eq(self.inputa - self.inputb - self.PSW.C),
h.eq(self.inputa[:4] - self.inputb[:4] - self.PSW.C),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self.result == f[:8]),
Assert(self._psw.N == f[7]),
Assert(self._psw.V == (f[7] ^ f[8])),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == h[4]),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(f[:8].bool())),
Assert(self._psw.C == f[8]),
]
with m.Case(Operation.CMP):
full = Cat(self.result, self._psw.C)
m.d.comb += [
full.eq(self.inputa.as_signed() - self.inputb.as_signed()),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
self._psw.V.eq(self.result[7] != self._psw.C),
]
if self.verification is Operation.CMP:
r = Signal(9)
m.d.comb += r.eq(self.inputa.as_signed() -
self.inputb.as_signed())
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r[:8]),
Assert(self._psw.N == r[7]),
Assert(self._psw.V == (r[7] ^ r[8])),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r[:8].bool())),
Assert(self._psw.C == r[8]),
]
with m.Case(Operation.AND):
m.d.comb += [
self.result.eq(self.inputa & self.inputb),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.AND:
r = Signal(8)
m.d.comb += r.eq(self.inputa & self.inputb)
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == r[7]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.PSW.C),
]
with m.Case(Operation.OOR):
m.d.comb += [
self.result.eq(self.inputa | self.inputb),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.OOR:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa | self.inputb),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == r[7]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.PSW.C),
]
with m.Case(Operation.EOR):
m.d.comb += [
self.result.eq(self.inputa ^ self.inputb),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.EOR:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa ^ self.inputb),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == r[7]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.PSW.C),
]
with m.Case(Operation.INC):
m.d.comb += [
self.result.eq(self.inputa + 1),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.INC:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa + 1),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == r[7]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.PSW.C),
]
with m.Case(Operation.DEC):
m.d.comb += [
self.result.eq(self.inputa - 1),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.DEC:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa - 1),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == r[7]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.PSW.C),
]
with m.Case(Operation.ASL):
m.d.comb += [
Cat(self.result,
self._psw.C).eq(Cat(Const(0), self.inputa)),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.ASL:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa * 2),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == self.inputa[6]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.inputa[7]),
]
with m.Case(Operation.LSR):
m.d.comb += [
Cat(self._psw.C,
self.result).eq(Cat(self.inputa, Const(0))),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.LSR:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa // 2),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == 0),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.inputa[0]),
]
with m.Case(Operation.ROL):
m.d.comb += [
Cat(self.result,
self._psw.C).eq(Cat(self.PSW.C, self.inputa)),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.ROL:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa * 2 + self.PSW.C),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == self.inputa[6]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.inputa[7]),
]
with m.Case(Operation.ROR):
m.d.comb += [
Cat(self._psw.C,
self.result).eq(Cat(self.inputa, self.PSW.C)),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.ROR:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa // 2 + Cat(Signal(7), self.PSW.C)),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == self.PSW.C),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r.bool())),
Assert(self._psw.C == self.inputa[0]),
]
with m.Case(Operation.XCN):
m.d.comb += [
self.result.eq(Cat(self.inputa[4:], self.inputa[:4])),
self._psw.N.eq(self.result.as_signed() < 0),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.XCN:
r = Signal(8)
m.d.comb += [
r.eq(self.inputa * 16 + self.inputa // 16),
]
with m.If(~Initial()):
m.d.comb += [
Assert(self.result == r),
Assert(self._psw.N == self.inputa[3]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(self.inputa.bool())),
Assert(self._psw.C == self.PSW.C),
]
with m.Case(Operation.DAA):
temp = Signal().like(self.inputa)
with m.If(self.PSW.C | (self.inputa > 0x99)):
m.d.comb += self._psw.C.eq(1)
m.d.comb += temp.eq(self.inputa + 0x60)
with m.Else():
m.d.comb += temp.eq(self.inputa)
with m.If(self.PSW.H | (temp[:4] > 0x09)):
m.d.comb += self.result.eq(temp + 0x06)
m.d.comb += [
self._psw.N.eq(self.result & 0x80),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.DAA:
with m.If(~Initial()):
m.d.comb += [Assert(False)]
with m.Case(Operation.DAS):
temp = Signal().like(self.inputa)
with m.If(~self.PSW.C | (self.inputa > 0x99)):
m.d.comb += self._psw.C.eq(0)
m.d.comb += temp.eq(self.inputa - 0x60)
with m.Else():
m.d.comb += temp.eq(self.inputa)
with m.If(~self.PSW.H | (temp[:4] > 0x09)):
m.d.comb += self.result.eq(temp - 0x06)
m.d.comb += [
self._psw.N.eq(self.result & 0x80),
self._psw.Z.eq(self.result == 0),
]
if self.verification is Operation.DAS:
with m.If(~Initial()):
m.d.comb += [Assert(False)]
# could be optimized with shift to right
with m.Case(Operation.MUL):
with m.Switch(self.count):
for i in range(0, 8):
with m.Case(i):
prod = self.inputa * self.inputb[i]
if i == 0:
prod = Cat(prod[0:7], ~prod[7], Const(1))
elif i == 7:
prod = Cat(~prod[0:7], prod[7], Const(1))
else:
prod = Cat(prod[0:7], ~prod[7])
m.d.sync += self.partial.eq(self.partial +
(prod << i))
m.d.sync += self.count.eq(i + 1)
with m.Case(8):
m.d.sync += self.partial_hi.eq(self.partial_lo)
m.d.sync += self.count.eq(9)
m.d.comb += [
self.result.eq(self.partial_hi),
self._psw.N.eq(self.partial_hi.as_signed() < 0),
self._psw.Z.eq(self.partial_hi == 0),
]
with m.Case(9):
m.d.sync += self.partial.eq(0)
m.d.sync += self.count.eq(0)
m.d.comb += [
self.result.eq(self.partial_hi),
]
if self.verification is Operation.MUL:
r = Signal(16)
m.d.comb += [
r.eq(self.inputa.as_signed() *
self.inputb.as_signed()),
Cover(self.count == 9),
]
with m.If(self.count == 9):
m.d.comb += [
Assert(Past(self.result) == r[8:16]),
Assert(self.result == r[0:8]),
Assert(self._psw.N == r[15]),
Assert(self._psw.V == self.PSW.V),
Assert(self._psw.P == self.PSW.P),
Assert(self._psw.B == self.PSW.B),
Assert(self._psw.H == self.PSW.H),
Assert(self._psw.I == self.PSW.I),
Assert(self._psw.Z == ~(r[8:16].bool())),
Assert(self._psw.C == self.PSW.C),
]
with m.If(~Initial() & (self.count == 0)):
m.d.comb += [
Assert(self.partial == 0),
Assert((Past(self.count) == 0)
| (Past(self.count) == 9)),
]
with m.If(~Initial() & (self.count != 0)):
m.d.comb += [
Assert(self.count == Past(self.count) + 1),
Assume(self.inputa == Past(self.inputa)),
Assume(self.inputb == Past(self.inputb)),
]
with m.Case(Operation.DIV):
over = Signal(reset=0)
with m.Switch(self.count):
with m.Case(0):
m.d.sync += self.partial_hi.eq(self.inputa) # Y
m.d.sync += self.count.eq(1)
with m.Case(1):
m.d.sync += self.partial_lo.eq(self.inputa) # A
m.d.sync += self.count.eq(2)
m.d.comb += self._psw.H.eq(
Mux(self.partial_hi[0:4] >= self.inputb[0:4], 1,
0))
for i in range(2, 11):
with m.Case(i):
tmp1_w = Cat(self.partial << 1, over)
tmp1_x = Signal(17)
tmp1_y = Signal(17)
tmp1_z = Signal(17)
tmp2 = self.inputb << 9
m.d.comb += tmp1_x.eq(tmp1_w)
with m.If(tmp1_w & 0x20000):
m.d.comb += tmp1_x.eq((tmp1_w & 0x1FFFF) | 1)
m.d.comb += tmp1_y.eq(tmp1_x)
with m.If(tmp1_x >= tmp2):
m.d.comb += tmp1_y.eq(tmp1_x ^ 1)
m.d.comb += tmp1_z.eq(tmp1_y)
with m.If(tmp1_y & 1):
m.d.comb += tmp1_z.eq((tmp1_y - tmp2)
& 0x1FFFF)
m.d.sync += Cat(self.partial, over).eq(tmp1_z)
m.d.sync += self.count.eq(i + 1)
with m.Case(11):
m.d.sync += self.count.eq(12)
m.d.comb += [
self.result.eq(
(Cat(self.partial, over) >> 9)), # Y %
]
with m.Case(12):
m.d.sync += self.partial.eq(0)
m.d.sync += over.eq(0)
m.d.sync += self.count.eq(0)
m.d.comb += [
self.result.eq(self.partial_lo), # A /
self._psw.N.eq(self.partial_lo.as_signed() < 0),
self._psw.V.eq(over),
self._psw.Z.eq(self.partial_lo == 0),
]
if self.verification is Operation.DIV:
m.d.comb += [
Cover(self.count == 12),
]
with m.If(self.count == 12):
m.d.comb += [Assert(False)]
return m
def elaborate(self, platform):
if platform is not None:
platform.add_file("picorv32.v", open("picorv32.v", "r"))
if not os.path.exists("build"):
os.makedirs("build")
subprocess.run(
[
"cargo", "objcopy", "--release", "--", "-O", "binary",
"../build/app.bin"
],
cwd="app",
).check_returncode()
with open("build/app.bin", "rb") as f:
b = bytearray(f.read())
b.extend([0] * (4 - (len(b) % 4)))
app = np.frombuffer(b, dtype='<u4').tolist()
# MEM_SIZE = 256 # words
RAM_SIZE = 256 # words
init = ([0] * RAM_SIZE) + app
MEM_SIZE = len(init)
mem = Memory(
width=32,
depth=MEM_SIZE,
init=init,
)
resetn = Signal()
mem_valid = Signal()
mem_ready = Signal()
mem_addr = Signal(32)
mem_wdata = Signal(32)
mem_wstrb = Signal(4)
mem_rdata = Signal(32)
m = Module()
m.d.comb += resetn.eq(~ResetSignal())
m.submodules.picorv32 = Instance(
"picorv32",
p_ENABLE_COUNTERS=0,
p_LATCHED_MEM_RDATA=1,
p_TWO_STAGE_SHIFT=0,
p_TWO_CYCLE_ALU=1,
p_CATCH_MISALIGN=0,
p_CATCH_ILLINSN=0,
p_COMPRESSED_ISA=1,
p_ENABLE_MUL=1,
p_PROGADDR_RESET=1024,
p_PROGADDR_IRQ=1024 + 0x10,
i_clk=ClockSignal(),
i_resetn=resetn,
o_mem_valid=mem_valid,
i_mem_ready=mem_ready,
o_mem_addr=mem_addr,
o_mem_wdata=mem_wdata,
o_mem_wstrb=mem_wstrb,
i_mem_rdata=mem_rdata,
)
m.submodules.read_port = read_port = mem.read_port(transparent=False)
m.submodules.write_port = write_port = mem.write_port(granularity=8)
m.d.sync += mem_ready.eq(0)
m.d.comb += [
read_port.addr.eq(mem_addr >> 2),
mem_rdata.eq(read_port.data),
read_port.en.eq((~mem_wstrb).bool()),
write_port.addr.eq(mem_addr >> 2),
write_port.data.eq(mem_wdata),
write_port.en.eq(mem_wstrb),
]
with m.If(resetn & mem_valid & ~mem_ready):
with m.If((mem_addr >> 2) < MEM_SIZE):
m.d.sync += mem_ready.eq(1)
for mapping in self.memory_mappings:
if mapping.writing_enabled:
with m.If(mem_wstrb.bool() & (mem_addr == mapping.addr)):
if mapping.write is not None:
mapping.write(m, mem_wdata)
else:
m.d.sync += [
mapping.signal.eq(mem_wdata),
mem_ready.eq(1),
]
if mapping.read:
with m.If((~mem_wstrb).bool()
& (mem_addr == mapping.addr)):
m.d.comb += mem_rdata.eq(mapping.signal)
m.d.sync += mem_ready.eq(1)
if not mapping.read and not (mapping.write
or mapping.writing_enabled):
print(mapping.addr)
print("mapping doesn't specify read or write",
file=sys.stderr)
return m
