def listBoards(self):
xem = ok.FrontPanel()
self.moduleCount = xem.GetDeviceCount()
self.modules = dict()
for i in range(self.moduleCount):
serial = xem.GetDeviceListSerial(i)
tmp = ok.FrontPanel()
check(tmp.OpenBySerial(serial), "OpenBySerial")
desc = self.getDeviceDescription(tmp)
tmp = None
self.modules[desc.identifier] = desc
del (xem)
if self.openModule is not None:
self.modules[self.openModule.identifier] = self.openModule
return self.modules
def connectOKBoard(self):
fp = ok.FrontPanel()
module_count = fp.GetDeviceCount()
print "Found {} unused modules".format(module_count)
for i in range(module_count):
serial = fp.GetDeviceListSerial(i)
tmp = ok.FrontPanel()
tmp.OpenBySerial(serial)
iden = tmp.GetDeviceID()
if iden == self.okDeviceID:
self.xem = tmp
print 'Connected to {}'.format(iden)
self.programOKBoard()
return True
return False
def _initialize_fpga(self):
self.xem = ok.FrontPanel()
num_devices = self.xem.GetDeviceCount()
print_msg("Detected {} device{}".format(
num_devices, '' if num_devices == 2 else 's'))
if (num_devices == 0):
raise DeviceError
else:
# FIXME: Always opens the first device
serial = self.xem.GetDeviceListSerial(0)
if (self.xem.NoError != self.xem.OpenBySerial(serial)):
print_msg(
"FPGA with serial {} could not be opened".format(serial))
raise DeviceError
if (self.xem.NoError != self.xem.LoadDefaultPLLConfiguration()):
print_msg("Unable to set default PLL config")
raise DeviceError
if (self.xem.NoError != self.xem.ConfigureFPGA(PlusMaze.BITFILE)):
print_msg("Failed to load bitfile {}".format(PlusMaze.BITFILE))
raise DeviceError
else:
print_msg("Loaded bitfile {} to {}".format(
PlusMaze.BITFILE, serial))
def __init__(self, serial=None):
self.dev = ok.FrontPanel()
self.dev.OpenBySerial()
pll = ok.okCPLL22150()
self.dev.GetEepromPLL22150Configuration(pll)
self.dev.SetPLL22150Configuration(pll)
self.sampling_freq = pll.GetOutputFrequency(0)
def refresh_available_interfaces(self):
for device_id, device in self.interfaces.items():
try:
device.GetDeviceID()
except:
del self.interfaces[device_id]
fp = ok.FrontPanel()
device_count = fp.GetDeviceCount()
for i in range(device_count):
serial = fp.GetDeviceListSerial(i)
tmp = ok.FrontPanel()
tmp.OpenBySerial(serial)
device_id = tmp.GetDeviceID()
print(device_id)
tmp.LoadDefaultPLLConfiguration()
self.interfaces[device_id] = tmp
def renameBoard(self, serial, newname):
tmp = ok.FrontPanel()
tmp.OpenBySerial(serial)
oldname = tmp.GetDeviceID()
tmp.SetDeviceId(newname)
tmp.OpenBySerial(serial)
newname = tmp.GetDeviceID()
if newname != oldname:
self.modules[newname] = self.modules.pop(oldname)
def __init__(self):
self._xem = ok.FrontPanel()
self._xem.OpenBySerial(SERIALNUM)
self._xem.LoadDefaultPLLConfiguration()
self._xem.ConfigureFPGA(BITFILENAME)
msg = ('Device idVendor = ' + str(SERIALNUM) + ' not found')
# was it found?
if self._xem.IsFrontPanelEnabled() is not True:
raise ValueError(msg)
def connectOKBoard(self):
self.xem = None
fp = ok.FrontPanel()
module_count = fp.GetDeviceCount()
print "Found {} unused modules".format(module_count)
for i in range(module_count):
serial = fp.GetDeviceListSerial(i)
tmp = ok.FrontPanel()
tmp.OpenBySerial(serial)
id = tmp.GetDeviceID()
if id == okDeviceID:
self.xem = tmp
print 'Connected to {}'.format(id)
self.programOKBoard(self.xem)
return
print 'Not found {}'.format(okDeviceID)
print 'Will try again in {} seconds'.format(devicePollingPeriod)
reactor.callLater(devicePollingPeriod, self.connectOKBoard)
def __init__(self, serial='', channel_map={'ch0':0,'ch1':1,'ch2':2,'ch3':3,'ch4':4,'ch5':5,'ch6':6,'ch7':7,'ch8':8,'ch9':9,'ch10':10,'ch11':11,'ch12':12,'ch13':13,'ch14':14,'ch15':15,'ch16':16,'ch17':17,'ch18':18,'ch19':19,'ch20':20,'ch21':21,'ch22':22,'ch23':23}, core='12x8'):
self.serial = serial
self.channel_map = channel_map
self.xem = ok.FrontPanel()
self.open_usb()
self.load_core(core)
self.setResetValue(0x00000000)
self.reset()
self.checkUnderflow()
def __init__(self):
try:
self.xem = ok.FrontPanel()
self.xem.OpenBySerial(DEVICESERIAL)
print "Found device called %s" % (self.xem.GetDeviceID())
bitfile = './XEM6001_275bins.bit'
DEVICE = 'XEM6001'
print "Loading PLL config"
pll = ok.PLL22150()
self.xem.GetEepromPLL22150Configuration(pll)
print "FREQUENCY=%d" % (FREQUENCY)
pll.SetVCOParameters(int(FREQUENCY), 48)
pll.SetDiv1(pll.DivSrc_VCO, 4)
pll.SetDiv2(pll.DivSrc_VCO, 4)
pll.SetOutputSource(0, pll.ClkSrc_Div1By2)
pll.SetOutputSource(1, pll.ClkSrc_Div1By2)
for i in range(6):
pll.SetOutputEnable(i, (i == 0))
print "Ref is at %gMHz, PLL is at %gMHz" % (pll.GetReference(),
pll.GetVCOFrequency())
for i in range(6):
if (pll.IsOutputEnabled(i)):
print "Clock %d at %gMHz" % (i, pll.GetOutputFrequency(i))
print "Programming PLL"
self.xem.SetPLL22150Configuration(pll)
print "Programming FPGA with:", bitfile
if (self.xem.ConfigureFPGA(bitfile) < 0):
print "Programming failed. Quitting..."
sys.exit()
except Exception as e:
print "initialization error" + str(e)
sys.exit(1)
self.internal_state = {}
self.internal_state["Count"] = 0
self.internal_state["IntTime"] = 250 # in ms
self.internal_state["SampFreq"] = 300.0 # in MHz
self.internal_state["MMAmp"] = 0.0
self.internal_state["MMPhase"] = 0.0
self.internal_state["Data"] = 0
self.internal_state["DataState"] = False
self.internal_state["Background"] = True
self.internal_state["OverCount"] = False
self.used_bins = NBINS
self.clk_div = 1.0
self.background_count = 0.
# initialization
self.SampFreq(30.0)
self.IntTime(250)
def _open_interface(self, interface_id):
open = self._get_open_interfaces()
if interface_id in open:
raise InterfaceAlreadyOpen(interface_id)
fp = ok.FrontPanel()
error = fp.OpenBySerial(interface_id)
if error:
raise InterfaceNotAvailable(interface_id)
fp.LoadDefaultPLLConfiguration()
self.interfaces[interface_id] = fp
def openBySerial(self, serial):
logger = logging.getLogger(__name__)
if self.xem is None or not self.xem.IsOpen(
) or self.xem.GetSerialNumber() != serial:
logger.debug("Open Serial {0}".format(serial))
self.xem = ok.FrontPanel()
check(self.xem.OpenBySerial(serial),
"OpenBySerial '{0}'".format(serial))
self.openModule = self.getDeviceDescription(self.xem)
else:
logger.debug("Serial {0} is already open".format(serial))
return None
def __init__(self, serial=''):
xem = ok.FrontPanel()
if (xem.OpenBySerial(serial) != 0):
raise RuntimeError, 'Failed to open USB connection.'
PLL = ok.PLL22150()
xem.GetPLL22150Configuration(PLL)
PLL.SetVCOParameters(333,48) #set VCO to 333MHz
PLL.SetOutputSource(0,5) #clk0@166MHz
PLL.SetDiv1(1,6) #needs to be set for DIV1=3
PLL.SetOutputEnable(0,1)
logging.getLogger().info('Pulser base clock input (clk2xin, stage two): '+str(PLL.GetOutputFrequency(0)))
xem.SetPLL22150Configuration(PLL)
if (xem.ConfigureFPGA(bitfile) != 0):
raise RuntimeError, 'Failed to upload bit file to fpga.'
self.xem = xem
def __init__(self, parent, title):
wx.Frame.__init__(self,
parent,
title=title,
size=(200, 60),
style=wx.DEFAULT_FRAME_STYLE ^ wx.RESIZE_BORDER)
# Initialize FPGA
self.xem = ok.FrontPanel()
serial = self.xem.GetDeviceListSerial(0)
self.xem.OpenBySerial(serial)
self.xem.LoadDefaultPLLConfiguration()
self.xem.ConfigureFPGA('first.bit')
# Load the sounds
self.go_sound = pyglet.resource.media('go.wav', streaming=False)
self.nogo_sound = pyglet.resource.media('no-go.wav', streaming=False)
# Set up the GUI
box = wx.BoxSizer(wx.HORIZONTAL)
self.trial_type_cb = wx.ComboBox(self,
size=(60, -1),
style=wx.CB_READONLY,
choices=['go', 'no-go'],
value='go')
self.run_btn = wx.Button(self, label='Run trial')
self.run_btn.Bind(wx.EVT_BUTTON, self._start_trial)
box.Add(self.trial_type_cb, 1, wx.ALL | wx.EXPAND, 0)
box.Add(self.run_btn, 1, wx.ALL | wx.EXPAND, 0)
self.SetSizer(box)
# Set up for polling of the FPGA
self.poll_timer = wx.Timer(self)
self.Bind(wx.EVT_TIMER, self._trial_polling, self.poll_timer)
self.Show(True)
def go(self, c):
one_s = [128, 240, 250, 2]
all_hi = [255] * 8 + one_s
all_lo = [0] * 8 + one_s
stop = [0] * 12
fp = ok.FrontPanel()
fp.GetDeviceCount()
ser = fp.GetDeviceListSerial(0)
fp.OpenBySerial(ser)
fp.ConfigureFPGA(
'/home/srgang/labrad_tools.srq/ok_server/bit/digital_sequencer-v3.2.bit'
)
fp.SetWireInValue(0x00, 3)
fp.UpdateWireIns()
fp.WriteToPipeIn(0x80, bytearray((all_hi + all_lo) * 10 + stop))
fp.SetWireInValue(0x00, 1)
fp.UpdateWireIns()
fp._lock = DeferredLock()
self._open_xems[ser] = fp
# fp.SetWireInValue(0x01, 1)
# fp.UpdateWireIns()
self.fp = fp
import time
def _intToBuf(num):
'''
takes the integer representing the setting and returns the buffer string for dds programming
'''
#converts value to buffer string, i.e 128 -> \x00\x00\x00\x80
b = num % 256**2
arr = array.array('B', [b % 256, b // 256])
ans = arr.tostring()
return ans
# ans = 65536*(256*ord(buf[1])+ord(buf[0]))+(256*ord(buf[3])+ord(buf[2]))
xem = ok.FrontPanel()
xem.OpenBySerial("")
xem.GetDeviceID()
pll = ok.PLL22393()
xem.GetPLL22393Configuration(pll) ### load configuration
pll.SetPLLParameters(0,25,3,True) ### PLL VCO setting: f = 48*25/3 = 400 MHz
pll.SetOutputDivider(0,4) ### Output1: 400/4 = 100 MHz
pll.SetOutputDivider(1,4) ### Output2: 400/4 = 100 MHz
pll.SetOutputEnable(0, True) ### Enable output1
pll.SetOutputEnable(1, True) ### Enable output2
print pll.GetOutputFrequency(0)
print pll.GetOutputFrequency(1)
xem.SetPLL22393Configuration(pll) ### set PLL configuration
xem.ConfigureFPGA('pulser.bit')
def __init__(self):
try:
maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once
loadedBitfile = 1 #Bitfile not yet loaded
self.xem = ok.FrontPanel()
devices = self.xem.GetDeviceCount()
print "Found %d attached FPGAs" % (devices)
if (devices > 0):
if (self.xem.OpenBySerial(DEVICESERIAL) == 0):
print "Opened an FPGA known as %s" % (
self.xem.GetDeviceID())
print "Now loading PLL configuration..."
pll = ok.PLL22150()
self.xem.GetEepromPLL22150Configuration(pll)
pll.SetVCOParameters(
int(SYSTEMCLOCK),
24) # NOTE - make sure this gives the right frequency
pll.SetDiv1(pll.DivSrc_VCO, 4)
pll.SetOutputSource(0, pll.ClkSrc_Div1By2)
pll.SetOutputSource(1, pll.ClkSrc_Div1By2)
pll.SetOutputEnable(1, True)
print "System clock to be set @ %gMHz" % (
pll.GetOutputFrequency(0))
print "SPI clock to be set @ %gMHz" % (
pll.GetOutputFrequency(1))
self.xem.SetPLL22150Configuration(pll)
print "Loading the bitfile..."
attempts = 0
while (attempts <= maxLoadAttempts):
loadedBitfile = self.xem.ConfigureFPGA(BITFILE)
if (loadedBitfile == 0):
print "Bitfile loaded!"
break
attempts += 1
except Exception as e:
print "Initialization error" + str(e)
sys.exit(1)
try:
self.internal_state = {}
for i in range(8):
self.internal_state["QuADDaughterType_%i" % i] = "DAC"
self.internal_state["QuADDaughterOutputMode_%i" % i] = "Single"
self.internal_state["QuADDaughterRangeMode_%i" %
i] = "Positive"
self.internal_state["QuADDaughterSource_%i" % i] = "ADC0"
self.internal_state["QuADDaughterPositiveRail_%i" % i] = 5.0
self.internal_state["QuADDaughterNegativeRail_%i" % i] = 0.0
self.internal_state["QuADDaughterVoltage_%i" % i] = 0
for i in range(5):
self.internal_state["QuADFilterType_%i" % i] = "P"
self.internal_state["QuADFilterSource_%i" % i] = "ADC0"
self.internal_state["QuADFilterCutoff_%i" % i] = 20000.0
self.internal_state["QuADFilterGain_%i" % i] = 1.0
self.internal_state["QuADFilterOffset_%i" % i] = 0.0
self.internal_state["QuADRampAmplitude"] = 1.0
self.internal_state["QuADRampFrequency"] = 100.0
self.internal_state["QuADRampStatus"] = "Off"
#Populate functions
try:
for i, key in enumerate(self.internal_state):
if 'QuADDaughter' in key:
FuncID, ind = (key.split('QuADDaughter')[1]).split('_')
FuncID = 'self.' + FuncID
setattr(self,
key,
lambda x, self=self, ind=ind, FuncID=FuncID:
eval(FuncID)(ind, x))
elif 'QuADFilter' in key:
FuncID, ind = (key.split('QuAD')[1]).split('_')
FuncID = 'self.' + FuncID
setattr(self,
key,
lambda x, self=self, ind=ind, FuncID=FuncID:
eval(FuncID)(ind, x))
if DEBUG: print FuncID, ind
except Exception as e:
print 'ERROR in populating functions: \n\n', e
# Now run initialization methods to reach a common start state
print "Engaging default state..."
# All daughters initialize as DACs
self.setRegister(0x0000, 0x00)
# All daughters initialize into non_feedback mode
self.setRegister(0x0002, 0x00)
# Set all DACs into positive mode and write 0 V to each
for i in range(8):
self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"])
self.setRegister(0x0010 + 2 * i, 0x0002)
self.setRegister(0x0011 + 2 * i, 0x0020)
self.xem.ActivateTriggerIn(0x40, i)
# In positive mode, the code to set zero volts is 0x180000
self.setRegister(0x0010 + 2 * i, 0x0000)
self.setRegister(0x0011 + 2 * i, 0x0018)
self.xem.ActivateTriggerIn(0x40, i)
print "Writing 0.0 to DAC at position " + str(i)
# Set all of the feedback modes to positive only
self.setRegister(0x0004, 0x00)
#Set the rail voltages for each DAC
for i in range(8):
self.PositiveRail(
i, self.internal_state["QuADDaughterPositiveRail_%i" % i])
self.NegativeRail(
i, self.internal_state["QuADDaughterNegativeRail_%i" % i])
# Update each of the filters to the internal state configuration
# NOTE - need to replace configureFilter() here to get rid of the extra function
for i in range(5):
self.configureFilter(i, self.internal_state["QuADFilterType_%i"%i], \
self.internal_state["QuADFilterSource_%i"%i], self.internal_state["QuADFilterCutoff_%i"%i], \
self.internal_state["QuADFilterGain_%i"%i], self.internal_state["QuADFilterOffset_%i"%i])
#Add initialization for the ramp
self.QuADRampFrequency(self.internal_state["QuADRampFrequency"])
self.QuADRampAmplitude(self.internal_state["QuADRampAmplitude"])
self.QuADRampStatus(self.internal_state["QuADRampStatus"])
print "Default state set. Welcome to the QuADCon!"
#sanity checking...
#self.setRegister(0x0000, 0x01)
#self.setRegister(0x0084, 0x0010)
except Exception as e:
print 'Could not run intialize: \n\n', e
def __init__(self):
try:
maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once
loadedBitfile = 1 #Bitfile not yet loaded
self.xem = ok.FrontPanel()
devices = self.xem.GetDeviceCount()
print "Found %d attached FPGAs" % (devices)
if (devices > 0):
if (self.xem.OpenBySerial(DEVICESERIAL) == 0):
print "Opened an FPGA known as %s" % (
self.xem.GetDeviceID())
print "Now loading PLL configuration..."
pll = ok.PLL22150()
self.xem.GetEepromPLL22150Configuration(pll)
pll.SetVCOParameters(
int(FREQUENCY),
24) # NOTE - make sure this gives the right frequency
pll.SetDiv1(pll.DivSrc_VCO, 4)
pll.SetOutputSource(0, pll.ClkSrc_Div1By2)
pll.SetOutputSource(1, pll.ClkSrc_Div1By2)
pll.SetOutputEnable(1, True)
print "System clock to be set @ %gMHz" % (
pll.GetOutputFrequency(0))
print "SPI clock to be set @ %gMHz" % (
pll.GetOutputFrequency(1))
self.xem.SetPLL22150Configuration(pll)
print "Loading the bitfile..."
attempts = 0
while (attempts <= maxLoadAttempts):
loadedBitfile = self.xem.ConfigureFPGA(BITFILE)
if (loadedBitfile == 0):
print "Bitfile loaded!"
break
attempts += 1
except Exception as e:
print "Initialization error" + str(e)
sys.exit(1)
try:
self.internal_state = {}
for i in range(8):
self.internal_state["QuADDaughterType_%i" % i] = "DAC"
self.internal_state["QuADDaughterOutputMode_%i" % i] = "Single"
self.internal_state["QuADDaughterRangeMode_%i" %
i] = "Positive"
self.internal_state["QuADDaughterSource_%i" % i] = "ADC0"
self.internal_state["QuADDaughterPositiveRail_%i" % i] = 5.0
self.internal_state["QuADDaughterNegativeRail_%i" % i] = 0.0
self.internal_state["QuADDaughterVoltage_%i" % i] = 0
for i in range(5):
self.internal_state["QuADFilterType_%i" % i] = "P"
self.internal_state["QuADFilterSource_%i" % i] = "ADC0"
self.internal_state["QuADFilterCutoff_%i" % i] = 20000.0
self.internal_state["QuADFilterGain_%i" % i] = 1.0
self.internal_state["QuADFilterOffset_%i" % i] = 0.0
#Populate functions
try:
self.func_dict = {}
for i, key in enumerate(self.internal_state):
if 'QuADDaughter' in key:
FuncID, ind = (key.split('QuADDaughter')[1]).split('_')
FuncID = 'self.' + FuncID
if DEBUG: print FuncID, ind
setattr(self,
key,
lambda x, self=self, ind=ind, FuncID=FuncID:
eval(FuncID)(ind, x))
except Exception as e:
print 'ERROR in populating functions: \n\n', e
# Now run initialization methods to reach a common start state
print "Engaging default state..."
# All daughters initialize as DACs
self.setRegister(0x0000, 0x00)
# All daughters initialize into non_feedback mode
self.setRegister(0x0002, 0x00)
# Update DAC source registers and set each into binary offset mode; RBUF configured for unity
for i in range(8):
self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"])
self.setRegister(0x0010 + 2 * i, 0x0012)
self.setRegister(0x0011 + 2 * i, 0x0020)
self.xem.ActivateTriggerIn(0x40, i)
print "Setting DAC at position " + str(
i) + " to binary offset mode"
# NOTE - the following zeroing is not necessary if you start in positive only mode
# Write 0.0 volts to each of the DACs
#code = int((10.0)/20.0 * 2**20)
#code = code | 0x100000
#bottomBits = code & 0x00FFFF
#topBits = (code & 0xFF0000) >> 16
self.setRegister(0x0010 + 2 * i, 0x0000)
self.setRegister(0x0011 + 2 * i, 0x0010)
self.xem.ActivateTriggerIn(0x40, i)
print "Writing 0.0 to DAC at position " + str(i)
# Set all of the feedback modes to positive only
self.setRegister(0x0004, 0x00)
# Set all of the filters to the on state
# NOTE - I removed the control for the filter on/off; need to check this more thoroughly
#self.setRegister(0x0003, 0x003F)
# Update each of the filters to the internal state configuration
for i in range(5):
self.configureFilter(i, self.internal_state["QuADFilterType_%i"%i], \
self.internal_state["QuADFilterSource_%i"%i], self.internal_state["QuADFilterCutoff_%i"%i], \
self.internal_state["QuADFilterGain_%i"%i], self.internal_state["QuADFilterOffset_%i"%i])
print "Default state set. Welcome to the QuADCon!"
except Exception as e:
print 'Could not run intialize: \n\n', e
def __init__(self, passedmodule=0):
self.lock = threading.Lock()
xem = ok.FrontPanel()
module_count = xem.GetDeviceCount()
print "Found %d modules" % (module_count)
if (module_count == 0): raise DeviceError("No XEMS found!")
serial = [-1] * module_count
for i in range(module_count):
serial[i] = xem.GetDeviceListSerial(i)
tmp = ok.FrontPanel()
tmp.OpenBySerial(serial[i])
print "Module %d: XEM3001v%s.%s, ID: %s, serial #: %s " % (
i, tmp.GetDeviceMajorVersion(), tmp.GetDeviceMinorVersion(),
tmp.GetDeviceID(), tmp.GetSerialNumber())
tmp = None
if (module_count > 1):
if passedmodule != 0:
module = passedmodule
else:
print "Choose a module: "
module = int(raw_input())
else:
module = 0
print "module %d selected" % (module)
xem.OpenBySerial(serial[module])
print "Loading PLL config"
pll = ok.PLL22150()
xem.GetEepromPLL22150Configuration(pll)
pll.SetVCOParameters(200, 48)
pll.SetDiv1(pll.DivSrc_VCO, 4)
pll.SetDiv2(pll.DivSrc_VCO, 4)
pll.SetOutputSource(0, pll.ClkSrc_Div1By2)
for i in range(6):
pll.SetOutputEnable(i, (i == 0))
print "Ref is at %gMHz, PLL is at %gMHz" % (pll.GetReference(),
pll.GetVCOFrequency())
for i in range(6):
if (pll.IsOutputEnabled(i)):
print "Clock %d at %gMHz" % (i, pll.GetOutputFrequency(i))
print "Programming PLL"
#xem.SetEepromPLL22150Configuration(pll)
xem.SetPLL22150Configuration(pll)
print "Programming FPGA"
prog = xem.ConfigureFPGA('monocontroller.bit')
if (prog != 0):
print 'failed! code:', prog
raise
self.xem = xem
self.name = xem.GetDeviceID()
self.err1f = self.err3f = self.photodiode = self.trace = 0.0
self.netport = 13004
self.state = {
'DAC0wave': [0.0, 0.0, 200.0],
'DAC1wave': [0.0, 0.0, 200.0],
'FREQ': 0x07ae,
'DAC2wave': [0.0, 0.0, 200.0],
'DAC3wave': [0.0, 0.0, 200.0],
'DAC2wave': [0.0, 0.0, 200.0],
'DAC3wave': [0.0, 0.0, 200.0],
'DAC0lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0],
'DAC1lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0],
'DAC2lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0],
'DAC3lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0]
}
self.read_config()
print "Initialization of hardware done"
def __init__(self):
try:
maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once
loadedBitfile = 1 #Bitfile not yet loaded
self.xem = ok.FrontPanel()
devices = self.xem.GetDeviceCount()
print "Found %d attached FPGAs" % (devices)
if (devices > 0):
if (self.xem.OpenBySerial(DEVICESERIAL) == 0):
print "Opened an FPGA known as %s" % (
self.xem.GetDeviceID())
print "Now loading PLL configuration..."
pll = ok.PLL22150()
self.xem.GetEepromPLL22150Configuration(pll)
pll.SetVCOParameters(
int(FREQUENCY),
24) # NOTE - make sure this gives the right frequency
pll.SetDiv1(pll.DivSrc_VCO, 4)
pll.SetOutputSource(0, pll.ClkSrc_Div1By2)
pll.SetOutputSource(1, pll.ClkSrc_Div1By2)
pll.SetOutputEnable(1, True)
print "System clock to be set @ %gMHz" % (
pll.GetOutputFrequency(0))
print "SPI clock to be set @ %gMHz" % (
pll.GetOutputFrequency(1))
self.xem.SetPLL22150Configuration(pll)
print "Loading the bitfile..."
attempts = 0
while (attempts <= maxLoadAttempts):
loadedBitfile = self.xem.ConfigureFPGA(BITFILE)
if (loadedBitfile == 0):
print "Bitfile loaded!"
break
attempts += 1
except Exception as e:
print "Initialization error" + str(e)
sys.exit(1)
self.internal_state = {}
self.internal_state["QuAD674DaughterType"] = [
"DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC"
]
self.internal_state["QuAD674DaughterOutputMode"] = [
"Single", "Single", "Single", "Single", "Single", "Single",
"Single", "Single"
]
self.internal_state["QuAD674DaughterRangeMode"] = [
"Positive", "Positive", "Positive", "Positive", "Positive",
"Positive", "Positive", "Positive"
]
self.internal_state["QuAD674DaughterSource"] = [
"ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0"
]
self.internal_state['QuAD674DaughterPositiveRail'] = [
5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0
]
self.internal_state['QuAD674DaughterNegativeRail'] = [
0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0
]
self.internal_state["QuAD674DaughterVoltage"] = [
0, 0, 0, 0, 0, 0, 0, 0
]
self.internal_state["QuAD674FilterType"] = [
"P", "P", "P", "P", "P", "P"
]
self.internal_state["QuAD674FilterSource"] = [
"ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0"
]
self.internal_state["QuAD674FilterCutoff"] = [
20000.0, 20000.0, 20000.0, 20000.0, 20000.0, 20000.0
]
self.internal_state["QuAD674FilterGain"] = [
1.0, 1.0, 1.0, 1.0, 1.0, 1.0
]
self.internal_state["QuAD674FilterOffset"] = [
0.0, 0.0, 0.0, 0.0, 0.0, 0.0
]
# Private internal states for distinguishing ADC voltages from DAC voltages
self.internal_state["DACVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0]
self.internal_state["ADCVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0]
#Stuff for testing the scope interface
self.internal_state["SCOPEDATA"] = [[0, 0], [1, 1], [1, 2]]
#Settings for the ramp controller
self.internal_state["QuAD674RampTarget"] = "DAC0"
self.internal_state["QuAD674RampFrequency"] = 1000.0
self.internal_state["QuAD674RampStatus"] = "Off"
# Now run initialization methods to reach a common start state
print "Engaging default state..."
# All daughters initialize as DACs
self.setRegister(0x0000, 0x00)
# All daughters initialize into non-feedback mode
self.setRegister(0x0002, 0x00)
# Update DAC source registers and set each into binary offset mode; RBUF configured for unity
#ISSUE - Here is where I need to change the initialization into binary offset mode
for i in range(8):
self.setDaughterRails(i, self.internal_state['QuAD674DaughterNegativeRail'][i], \
self.internal_state['QuAD674DaughterPositiveRail'][i])
self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"])
self.setRegister(0x0010 + 2 * i, 0x0002)
self.setRegister(0x0011 + 2 * i, 0x0020)
self.xem.ActivateTriggerIn(0x40, i)
print "Setting DAC at position " + str(
i) + " to twos complement mode"
self.setRegister(0x0010 + 2 * i, 0x0000)
self.setRegister(0x0011 + 2 * i, 0x0018)
self.xem.ActivateTriggerIn(0x40, i)
print "Writing 0.0 to DAC at position " + str(i)
# Set all of the feedback modes to positive only
self.setRegister(0x0004, 0x00)
# Set all of the filters to the on state
# ISSUE - I removed the control for the filter on/off; need to check this more thoroughly
#self.setRegister(0x0003, 0x003F)
# Update each of the filters to the internal state configuration
for i in range(5):
self.configureFilter(i, self.internal_state["QuAD674FilterType"][i], \
self.internal_state["QuAD674FilterSource"][i], self.internal_state["QuAD674FilterCutoff"][i], \
self.internal_state["QuAD674FilterGain"][i], self.internal_state["QuAD674FilterOffset"][i])
# Update the ramp to the internal state configuration
self.configureRamp(self.internal_state["QuAD674RampTarget"],
self.internal_state["QuAD674RampFrequency"])
print "Default state set. Welcome to the QuAD674Con!"
def __init__(self):
try:
maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once
loadedBitfile = 1 #Bitfile not yet loaded
self.xem = ok.FrontPanel()
devices = self.xem.GetDeviceCount()
print "Found %d attached FPGAs" % (devices)
if (devices > 0):
if (self.xem.OpenBySerial(DEVICESERIAL) == 0):
print "Opened an FPGA known as %s" % (
self.xem.GetDeviceID())
print "Now loading PLL configuration..."
pll = ok.PLL22150()
self.xem.GetEepromPLL22150Configuration(pll)
pll.SetVCOParameters(
int(FREQUENCY),
24) # NOTE - make sure this gives the right frequency
pll.SetDiv1(pll.DivSrc_VCO, 4)
pll.SetOutputSource(0, pll.ClkSrc_Div1By2)
pll.SetOutputSource(1, pll.ClkSrc_Div1By2)
pll.SetOutputEnable(1, True)
print "System clock to be set @ %gMHz" % (
pll.GetOutputFrequency(0))
print "SPI clock to be set @ %gMHz" % (
pll.GetOutputFrequency(1))
self.xem.SetPLL22150Configuration(pll)
print "Loading the bitfile..."
attempts = 0
while (attempts <= maxLoadAttempts):
loadedBitfile = self.xem.ConfigureFPGA(BITFILE)
if (loadedBitfile == 0):
print "Bitfile loaded!"
break
attempts += 1
except Exception as e:
print "Initialization error" + str(e)
sys.exit(1)
self.internal_state = {}
self.internal_state["QuADDaughterType"] = [
"DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC"
]
self.internal_state["QuADDaughterOutputMode"] = [
"Single", "Single", "Single", "Single", "Single", "Single",
"Single", "Single"
]
self.internal_state["QuADDaughterRangeMode"] = [
"Positive", "Positive", "Positive", "Positive", "Positive",
"Positive", "Positive", "Positive"
]
self.internal_state["QuADDaughterSource"] = [
"ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0"
]
self.internal_state['QuADDaughterPositiveRail'] = [
5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0
]
self.internal_state['QuADDaughterNegativeRail'] = [
0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0
]
self.internal_state["QuADDaughterVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0]
self.internal_state["QuADFilterType"] = ["P", "P", "P", "P", "P", "P"]
self.internal_state["QuADFilterSource"] = [
"ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0"
]
self.internal_state["QuADFilterCutoff"] = [
20000.0, 20000.0, 20000.0, 20000.0, 20000.0, 20000.0
]
self.internal_state["QuADFilterGain"] = [1.0, 1.0, 1.0, 1.0, 1.0, 1.0]
self.internal_state["QuADFilterOffset"] = [
0.0, 0.0, 0.0, 0.0, 0.0, 0.0
]
# Private internal states for distinguishing ADC voltages from DAC voltages
self.internal_state["DACVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0]
self.internal_state["ADCVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0]
# Private internal states for controlling ouptut statuses
#self.internal_state["RBUF"] = 0xFF #state of the ouput amplifier; controls the output rails
#self.internal_state["2CM
# Now run initialization methods to reach a common start state
print "Engaging default state..."
# All daughters initialize as DACs
self.setRegister(0x0000, 0x00)
# All daughters initialize into non-feedback mode
self.setRegister(0x0002, 0x00)
# Update DAC source registers and set each into binary offset mode; RBUF configured for unity
for i in range(8):
self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"])
self.setRegister(0x0010 + 2 * i, 0x0012)
self.setRegister(0x0011 + 2 * i, 0x0020)
self.xem.ActivateTriggerIn(0x40, i)
print "Setting DAC at position " + str(
i) + " to binary offset mode"
# NOTE - the following zeroing is not necessary if you start in positive only mode
# Write 0.0 volts to each of the DACs
#code = int((10.0)/20.0 * 2**20)
#code = code | 0x100000
#bottomBits = code & 0x00FFFF
#topBits = (code & 0xFF0000) >> 16
self.setRegister(0x0010 + 2 * i, 0x0000)
self.setRegister(0x0011 + 2 * i, 0x0010)
self.xem.ActivateTriggerIn(0x40, i)
print "Writing 0.0 to DAC at position " + str(i)
# Set all of the feedback modes to positive only
self.setRegister(0x0004, 0x00)
# Set all of the filters to the on state
# NOTE - I removed the control for the filter on/off; need to check this more thoroughly
#self.setRegister(0x0003, 0x003F)
# Update each of the filters to the internal state configuration
for i in range(5):
self.configureFilter(i, self.internal_state["QuADFilterType"][i], \
self.internal_state["QuADFilterSource"][i], self.internal_state["QuADFilterCutoff"][i], \
self.internal_state["QuADFilterGain"][i], self.internal_state["QuADFilterOffset"][i])
print "Default state set. Welcome to the QuADCon!"
for i in range(samples):
total = total + data[i]
samp = samp + data[i]*math.sin(2*i*math.pi*f/100./oversample)
camp = camp + data[i]*math.cos(2*i*math.pi*f/100./oversample)
if camp == 0: phase = 0
else: phase = math.atan(samp/camp)
amp = math.sqrt(samp**2 + camp**2)
if total == 0: fft[f,0] = 0
else: fft[f,0] = amp/total
fft[f,1] = phase
return fft
xem = ok.FrontPanel()
module_count = xem.GetDeviceCount()
print "Found %d modules"%(module_count)
if (module_count == 0): raise "No XEMs found!"
for i in range(module_count):
serial = xem.GetDeviceListSerial(i)
tmp = ok.FrontPanel()
tmp.OpenBySerial(serial)
id = tmp.GetDeviceID()
tmp = None
if (id == 'Photon Counter'):
break
if (id != 'Photon Counter'):
raise "Didn't find Photon Counter in module list!"
def openByName(self, name):
self.xem = ok.FrontPanel()
check(self.xem.OpenBySerial(self.modules[name].serial),
"OpenByName {0}".format(name))
return self.xem
return int(tuningword[0:16],2), int(tuningword[16:32],2)
def cselect(dds, channel, multiplier, vcogain):
#Generate words for channel selection and clock configuration
x1 = ["0"]*8
x1[3 - channel] = "1"
x2 = "{0:05b}".format(multiplier)
x3 = str(1*vcogain)
x4 = "{0:02b}".format(dds + 1)
x = "".join(x1) + x2 + x3 + x4
return int(x,2)
import ok
from time import sleep
fp = ok.FrontPanel()
print("There are {} connected OpalKelly device(s).".format(fp.GetDeviceCount()))
serialno = fp.GetDeviceListSerial(0)
fp.OpenBySerial(serialno)
print("Opened communications with " + fp.GetDeviceID() +'.')
x = fp.ConfigureFPGA("./dds3_ad9959.bit")
for k in channels:
tuningword = freq2word(float(k['frequency']), clock*multiplier)
ep02, ep01 = wordsplit(tuningword)
ep00 = cselect(k['address'][0],k['address'][1],multiplier,vcogain)
print("{0} MHz written to {1}".format(k['frequency'],k['name']))
