def on_activate(self): """ Connect and configure the access to the FPGA. """ # Create an instance of the Opal Kelly FrontPanel. The Frontpanel is a # c dll which was wrapped with SWIG for Windows type systems to be # accessed with python 3.4. You have to ensure to use the python 3.4 # version to be able to run the Frontpanel wrapper: self._fpga = ok.FrontPanel() # threading self.threadlock = Mutex() # TTL output status of the 8 channels self._switch_status = { 1: False, 2: False, 3: False, 4: False, 5: False, 6: False, 7: False, 8: False } self._connected = False # connect to the FPGA module self._connect() return
def on_activate(self): """ Connect and configure the access to the FPGA. """ # Create an instance of the Opal Kelly FrontPanel. The Frontpanel is a # c dll which was wrapped with SWIG for Windows type systems to be # accessed with python 3.4. You have to ensure to use the python 3.4 # version to be able to run the Frontpanel wrapper: self._fpga = ok.FrontPanel() # TTL output status of the 8 channels self._switch_status = {chnl: False for chnl in range(8)} self._connected = False # Sanity check for fpga_type ConfigOption self._fpga_type = self._fpga_type.upper() if self._fpga_type not in ('XEM6310_LX45', 'XEM6310_LX150'): self.log.error( 'Unsupported FPGA type "{0}" specified in config. Valid options are ' '"XEM6310_LX45" and "XEM6310_LX150".\nAborting module activation.' ''.format(self._fpga_type)) return # connect to the FPGA module self._connect() return
def on_activate(self): """ Connect and configure the access to the FPGA. """ config = self.getConfiguration() self._switching_voltage = {1: 0.5, 2: 0.5, 3: 0.5, 4: 0.5, 5: 0.5, 6: 0.5, 7: 0.5, 8: 0.5} for key in config.keys(): if 'threshV_ch' in key: self._switching_voltage[int(key[-1])] = config[key] # fast counter state self.statusvar = -1 # fast counter parameters to be configured. Default values. self._binwidth = 1 # number of elementary bins to be combined into a single bin self._gate_length_bins = 8192 # number of bins in one gate (max 65536) self._number_of_gates = 1 # number of gates in the pulse sequence (max 512) self._old_data = None # histogram to be added to the current data after # continuing a measurement self.count_data = None self.saved_count_data = None # Count data stored to continue measurement # Create an instance of the Opal Kelly FrontPanel. The Frontpanel is a C dll which was # wrapped for use with python. self._fpga = ok.FrontPanel() # connect to the FPGA module self._connect() # configure DAC for threshold voltages self._reset_dac() self._activate_dac_ref() self._set_dac_voltages() return
def on_activate(self): """ Connect and configure the access to the FPGA. """ self._switching_voltage = { 1: self._threshold_ch1, 2: self._threshold_ch2, 3: self._threshold_ch3, 4: self._threshold_ch4, 5: self._threshold_ch5, 6: self._threshold_ch6, 7: self._threshold_ch7, 8: self._threshold_ch8 } # fast counter state self._statusvar = -1 # fast counter parameters to be configured. Default values. self._binwidth = 1 # number of elementary bins to be combined into a single bin self._gate_length_bins = 8192 # number of bins in one gate (max 65536) self._number_of_gates = 1 # number of gates in the pulse sequence (max 512) self.count_data = None self.saved_count_data = None # Count data stored to continue measurement # Create an instance of the Opal Kelly FrontPanel. The Frontpanel is a C dll which was # wrapped for use with python. self._fpga = ok.FrontPanel() # connect to the FPGA module self._connect() # configure DAC for threshold voltages self._reset_dac() self._activate_dac_ref() self._set_dac_voltages() return
def on_activate(self): self.fp = ok.FrontPanel() self.fp.GetDeviceCount() self.fp.OpenBySerial(self.fp.GetDeviceListSerial(0)) self.fp.ConfigureFPGA( os.path.join(self.get_main_dir(), 'thirdparty', 'qo_fpga', 'switch_top.bit')) if not self.fp.IsFrontPanelEnabled(): self.log.error('FrontPanel is not enabled in FPGA switch!') return else: self.reset() self.log.info('FPGA connected')
def __init__(self, config, **kwargs): super().__init__(config=config, **kwargs) self.log.info('The following configuration was found.') for key in config.keys(): self.log.info('{0}: {1}'.format(key, config[key])) # Create an instance of the Opal Kelly FrontPanel. The Frontpanel is a # c dll which was wrapped with SWIG for Windows type systems to be # accessed with python 3.4. You have to ensure to use the python 3.4 # version to be able to run the Frontpanel wrapper: self._fpga = ok.FrontPanel() self._internal_clock_hz = 950e6 # that is a fixed number, 950MHz self.statusvar = -1 # fast counter state
def on_activate(self): """ Connect and configure the access to the FPGA. """ config = self.getConfiguration() if 'fpga_serial' in config.keys(): self._serial = config['fpga_serial'] else: self.log.error( 'No parameter "fpga_serial" specified in the config! Set the ' 'serial number for the currently used fpga counter!\nOpen the Opal ' 'Kelly Frontpanel to obtain the serial number of the connected FPGA.\n' 'Do not forget to close the Frontpanel before starting the Qudi program.' ) # Create an instance of the Opal Kelly FrontPanel. The Frontpanel is a # c dll which was wrapped with SWIG for Windows type systems to be # accessed with python 3.4. You have to ensure to use the python 3.4 # version to be able to run the Frontpanel wrapper: self._fpga = ok.FrontPanel() # threading self.threadlock = Mutex() # TTL output status of the 8 channels self._switch_status = { 1: False, 2: False, 3: False, 4: False, 5: False, 6: False, 7: False, 8: False } self._connected = False # connect to the FPGA module self._connect() return
def on_activate(self): """ Connect and configure the access to the FPGA. """ self._switches = self._chk_refine_available_switches(self._switches) # Create an instance of the Opal Kelly FrontPanel self._fpga = ok.FrontPanel() # Sanity check for fpga_type ConfigOption self._fpga_type = self._fpga_type.upper() if self._fpga_type not in ('XEM6310_LX45', 'XEM6310_LX150'): raise NameError('Unsupported FPGA type "{0}" specified in config. Valid options are ' '"XEM6310_LX45" and "XEM6310_LX150".\nAborting module activation.' ''.format(self._fpga_type)) # connect to the FPGA module self._connect() # reset states if requested, otherwise use the saved states if self._remember_states and isinstance(self._states, dict) and \ set(self._states) == set(self._switches): self._states = {switch: self._states[switch] for switch in self._switches} self.states = self._states else: self._states = dict() self.states = {switch: states[0] for switch, states in self._switches.items()}
def on_activate(self): self.__samples_written = 0 self.__currently_loaded_waveform = '' self.fpga = ok.FrontPanel() self._connect_fpga() self.set_sample_rate(self.__sample_rate)
def on_activate(self): self.current_loaded_asset = '' self.fpga = ok.FrontPanel() self._connect_fpga() self.sample_rate = self.get_sample_rate()