def parse(tkns):
""" Parse a verilog module
module :=
'module' identifier [module_param_port_list] [list_of_ports]
';' {module_item} 'endmodule'
| 'module' identifier [module_param_port_list]
[list_of_port_declarations] ';' {non_port_module_item}
'endmodule'
"""
tkns.expect(Tokens.KW_MODULE)
# get module name
name = tkns.current().text
tkns.expect(Tokens.IDENTIFIER)
# get parameter port list, if it exists
params = []
if tkns.check(Tokens.HASH):
params = Parameter.parse_module_param_port_list(tkns)
# get i/o port list, if it exists
io = []
if tkns.check(Tokens.OPEN_PAREN):
if tkns.peek(Tokens.CLOSE_PAREN):
tkns.next()
tkns.next()
elif tkns.peek(Tokens.KW_INOUT) or tkns.peek(Tokens.KW_INPUT) or tkns.peek(Tokens.KW_OUTPUT):
io = Port.parse_list_of_port_declarations(tkns)
else:
io = Port.parse_list_of_ports(tkns)
# get module contents
# TODO: look at contents for more parameters, do other parsing
contents = []
while not tkns.accept(Tokens.KW_ENDMODULE):
contents.append(tkns.next())
return Module(name, params, io, contents)
