def connect(self, id_0, id_1, pat, int_0=0, int_1=1, compat_check=True): if not isinstance(pat, Pattern): raise ValueError('pat is not a Pattern instance') if id_0 not in self.rank_to_id.values(): raise ValueError('unrecognized module id %s' % id_0) if id_1 not in self.rank_to_id.values(): raise ValueError('unrecognized module id %s' % id_1) if not (int_0 in pat.interface_ids and int_1 in pat.interface_ids): raise ValueError('unrecognized pattern interface identifiers') self.log_info('connecting modules {0} and {1}'.format(id_0, id_1)) # Check compatibility of the interfaces exposed by the modules and the # pattern; since the manager only contains module classes and not class # instances, we need to create Interface instances from the selectors # associated with the modules in order to test their compatibility: if compat_check: rank_0 = self.rank_to_id.inv[id_0] rank_1 = self.rank_to_id.inv[id_1] self.log_info('checking compatibility of modules {0} and {1} and' ' assigned pattern'.format(id_0, id_1)) mod_int_0 = Interface(self._kwargs[rank_0]['sel']) mod_int_0[self._kwargs[rank_0]['sel']] = 0 mod_int_1 = Interface(self._kwargs[rank_1]['sel']) mod_int_1[self._kwargs[rank_1]['sel']] = 0 mod_int_0[self._kwargs[rank_0]['sel_in'], 'io'] = 'in' mod_int_0[self._kwargs[rank_0]['sel_out'], 'io'] = 'out' mod_int_0[self._kwargs[rank_0]['sel_gpot'], 'type'] = 'gpot' mod_int_0[self._kwargs[rank_0]['sel_spike'], 'type'] = 'spike' mod_int_1[self._kwargs[rank_1]['sel_in'], 'io'] = 'in' mod_int_1[self._kwargs[rank_1]['sel_out'], 'io'] = 'out' mod_int_1[self._kwargs[rank_1]['sel_gpot'], 'type'] = 'gpot' mod_int_1[self._kwargs[rank_1]['sel_spike'], 'type'] = 'spike' if not mod_int_0.is_compatible(0, pat.interface, int_0, True): raise ValueError('module %s interface incompatible ' 'with pattern interface %s' % (id_0, int_0)) if not mod_int_1.is_compatible(0, pat.interface, int_1, True): raise ValueError('module %s interface incompatible ' 'with pattern interface %s' % (id_1, int_1)) # XXX Need to check for fan-in XXX # Store the pattern information in the routing table: self.log_info('updating routing table with pattern') if pat.is_connected(0, 1): self.routing_table[id_0, id_1] = { 'pattern': pat, 'int_0': int_0, 'int_1': int_1 } if pat.is_connected(1, 0): self.routing_table[id_1, id_0] = { 'pattern': pat, 'int_0': int_1, 'int_1': int_0 } self.log_info('connected modules {0} and {1}'.format(id_0, id_1))
def __init__(self, sel, sel_in, sel_out, sel_gpot, sel_spike, data_gpot, data_spike, columns=['interface', 'io', 'type'], ctrl_tag=CTRL_TAG, gpot_tag=GPOT_TAG, spike_tag=SPIKE_TAG, id=None, device=None, routing_table=None, rank_to_id=None, pm_all=None, debug=False, time_sync=False): # Call super for BaseModule rather than Module because most of the # functionality of the former's constructor must be overridden in any case: super(BaseModule, self).__init__(ctrl_tag) self.debug = debug self.time_sync = time_sync self.device = device self._gpot_tag = gpot_tag self._spike_tag = spike_tag # Require several necessary attribute columns: assert 'interface' in columns assert 'io' in columns assert 'type' in columns self._init_gpu() # This is needed to ensure that MPI_Finalize is called before PyCUDA # attempts to clean up; see # https://groups.google.com/forum/#!topic/mpi4py/by0Rd5q0Ayw atexit.register(MPI.Finalize) # Manually register the file close method associated with MPIOutput # so that it is called by atexit before MPI.Finalize() (if the file is # closed after MPI.Finalize() is called, an error will occur): for k, v in twiggy.emitters.iteritems(): if isinstance(v._output, MPIOutput): atexit.register(v._output.close) # Ensure that the input and output port selectors respectively # select mutually exclusive subsets of the set of all ports exposed by # the module: assert SelectorMethods.is_in(sel_in, sel) assert SelectorMethods.is_in(sel_out, sel) assert SelectorMethods.are_disjoint(sel_in, sel_out) # Ensure that the graded potential and spiking port selectors # respectively select mutually exclusive subsets of the set of all ports # exposed by the module: assert SelectorMethods.is_in(sel_gpot, sel) assert SelectorMethods.is_in(sel_spike, sel) assert SelectorMethods.are_disjoint(sel_gpot, sel_spike) # Save routing table and mapping between MPI ranks and module IDs: self.routing_table = routing_table self.rank_to_id = rank_to_id # Save module interface data (stored in a dict of BasePortMapper instances): self.pm_all = pm_all # Generate a unique ID if none is specified: if id is None: self.id = uid() else: # Save routing table; if a unique ID was specified, it must be a node in # the routing table: if routing_table is not None and not routing_table.has_node(id): raise ValueError( 'routing table must contain specified module ID') self.id = id # Reformat logger name: LoggerMixin.__init__(self, 'mod %s' % self.id) # Create module interface given the specified ports: self.interface = Interface(sel, columns) # Set the interface ID to 0; we assume that a module only has one interface: self.interface[sel, 'interface'] = 0 # Set the port attributes: self.interface[sel_in, 'io'] = 'in' self.interface[sel_out, 'io'] = 'out' self.interface[sel_gpot, 'type'] = 'gpot' self.interface[sel_spike, 'type'] = 'spike' # Find the input and output ports: self.in_ports = self.interface.in_ports().to_tuples() self.out_ports = self.interface.out_ports().to_tuples() # Find the graded potential and spiking ports: self.gpot_ports = self.interface.gpot_ports().to_tuples() self.spike_ports = self.interface.spike_ports().to_tuples() self.in_gpot_ports = self.interface.in_ports().gpot_ports().to_tuples() self.in_spike_ports = self.interface.in_ports().spike_ports( ).to_tuples() self.out_gpot_ports = self.interface.out_ports().gpot_ports( ).to_tuples() self.out_spike_ports = self.interface.out_ports().spike_ports( ).to_tuples() # Set up mapper between port identifiers and their associated data: assert len(data_gpot) == len(self.gpot_ports) assert len(data_spike) == len(self.spike_ports) self.data = {} self.data['gpot'] = gpuarray.to_gpu(data_gpot) self.data['spike'] = gpuarray.to_gpu(data_spike) self.pm = {} self.pm['gpot'] = GPUPortMapper(sel_gpot, self.data['gpot'], make_copy=False) self.pm['spike'] = GPUPortMapper(sel_spike, self.data['spike'], make_copy=False)
def __init__(self, sel, sel_in, sel_out, sel_gpot, sel_spike, data_gpot, data_spike, columns=['interface', 'io', 'type'], port_data=PORT_DATA, port_ctrl=PORT_CTRL, port_time=PORT_TIME, id=None, device=None, debug=False, time_sync=False): self.debug = debug self.time_sync = time_sync self.device = device # Require several necessary attribute columns: assert 'interface' in columns assert 'io' in columns assert 'type' in columns # Generate a unique ID if none is specified: if id is None: id = uid() # Call super for BaseModule rather than Module because most of the # functionality of the former's constructor must be overridden in any case: super(BaseModule, self).__init__(port_ctrl, id) # Reformat logger name: LoggerMixin.__init__(self, 'mod %s' % self.id) # Data port: if port_data == port_ctrl: raise ValueError('data and control ports must differ') self.port_data = port_data if port_time == port_ctrl or port_time == port_data: raise ValueError('time port must differ from data and control ports') self.port_time = port_time # Initial network connectivity: self.net = 'none' # Create module interface given the specified ports: self.interface = Interface(sel, columns) # Set the interface ID to 0 # we assume that a module only has one interface: self.interface[sel, 'interface'] = 0 # Set port types: assert SelectorMethods.is_in(sel_in, sel) assert SelectorMethods.is_in(sel_out, sel) assert SelectorMethods.are_disjoint(sel_in, sel_out) self.interface[sel_in, 'io'] = 'in' self.interface[sel_out, 'io'] = 'out' assert SelectorMethods.is_in(sel_gpot, sel) assert SelectorMethods.is_in(sel_spike, sel) assert SelectorMethods.are_disjoint(sel_gpot, sel_spike) self.interface[sel_gpot, 'type'] = 'gpot' self.interface[sel_spike, 'type'] = 'spike' # Set up mapper between port identifiers and their associated data: assert len(data_gpot) == len(self.interface.gpot_ports()) assert len(data_spike) == len(self.interface.spike_ports()) self.data = {} self.data['gpot'] = data_gpot self.data['spike'] = data_spike self.pm = {} self.pm['gpot'] = PortMapper(sel_gpot, self.data['gpot']) self.pm['spike'] = PortMapper(sel_spike, self.data['spike']) # Patterns connecting this module instance with other modules instances. # Keyed on the IDs of those modules: self.patterns = {} # Each entry in pat_ints is a tuple containing the identifiers of which # of a pattern's identifiers are connected to the current module (first # entry) and the modules to which it is connected (second entry). # Keyed on the IDs of those modules: self.pat_ints = {} # Dict for storing incoming data; each entry (corresponding to each # module that sends input to the current module) is a deque containing # incoming data, which in turn contains transmitted data arrays. Deques # are used here to accommodate situations when multiple data from a # single source arrive: self._in_data = {} # List for storing outgoing data; each entry is a tuple whose first # entry is the source or destination module ID and whose second entry is # the data to transmit: self._out_data = [] # Dictionaries containing ports of source modules that # send output to this module. Must be initialized immediately before # an emulation begins running. Keyed on source module ID: self._in_port_dict = {} self._in_port_dict_ids = {} self._in_port_dict['gpot'] = {} self._in_port_dict['spike'] = {} # Dictionaries containing ports of destination modules that # receive input from this module. Must be initialized immediately before # an emulation begins running. Keyed on destination module ID: self._out_port_dict = {} self._out_port_dict_ids = {} self._out_port_dict['gpot'] = {} self._out_port_dict['spike'] = {} self._out_ids = [] self._in_ids = []
def __init__(self, sel, sel_in, sel_out, sel_gpot, sel_spike, data_gpot, data_spike, columns=['interface', 'io', 'type'], ctrl_tag=CTRL_TAG, gpot_tag=GPOT_TAG, spike_tag=SPIKE_TAG, id=None, device=None, routing_table=None, rank_to_id=None, debug=False, time_sync=False): super(Module, self).__init__(ctrl_tag) self.debug = debug self.time_sync = time_sync self.device = device self._gpot_tag = gpot_tag self._spike_tag = spike_tag # Require several necessary attribute columns: if 'interface' not in columns: raise ValueError('interface column required') if 'io' not in columns: raise ValueError('io column required') if 'type' not in columns: raise ValueError('type column required') # Initialize GPU here so as to be able to initialize a port mapper # containing GPU memory: self._init_gpu() # This is needed to ensure that MPI_Finalize is called before PyCUDA # attempts to clean up; see # https://groups.google.com/forum/#!topic/mpi4py/by0Rd5q0Ayw atexit.register(MPI.Finalize) # Manually register the file close method associated with MPIOutput # so that it is called by atexit before MPI.Finalize() (if the file is # closed after MPI.Finalize() is called, an error will occur): for k, v in twiggy.emitters.iteritems(): if isinstance(v._output, MPIOutput): atexit.register(v._output.close) # Ensure that the input and output port selectors respectively # select mutually exclusive subsets of the set of all ports exposed by # the module: if not SelectorMethods.is_in(sel_in, sel): raise ValueError('input port selector not in selector of all ports') if not SelectorMethods.is_in(sel_out, sel): raise ValueError('output port selector not in selector of all ports') if not SelectorMethods.are_disjoint(sel_in, sel_out): raise ValueError('input and output port selectors not disjoint') # Ensure that the graded potential and spiking port selectors # respectively select mutually exclusive subsets of the set of all ports # exposed by the module: if not SelectorMethods.is_in(sel_gpot, sel): raise ValueError('gpot port selector not in selector of all ports') if not SelectorMethods.is_in(sel_spike, sel): raise ValueError('spike port selector not in selector of all ports') if not SelectorMethods.are_disjoint(sel_gpot, sel_spike): raise ValueError('gpot and spike port selectors not disjoint') # Save routing table and mapping between MPI ranks and module IDs: self.routing_table = routing_table self.rank_to_id = rank_to_id # Generate a unique ID if none is specified: if id is None: self.id = uid() else: # If a unique ID was specified and the routing table is not empty # (i.e., there are connections between multiple modules), the id # must be a node in the routing table: if routing_table is not None and len(routing_table.ids) and \ not routing_table.has_node(id): raise ValueError('routing table must contain specified ' 'module ID: {}'.format(id)) self.id = id # Reformat logger name: LoggerMixin.__init__(self, 'mod %s' % self.id) # Create module interface given the specified ports: self.interface = Interface(sel, columns) # Set the interface ID to 0; we assume that a module only has one interface: self.interface[sel, 'interface'] = 0 # Set the port attributes: self.interface[sel_in, 'io'] = 'in' self.interface[sel_out, 'io'] = 'out' self.interface[sel_gpot, 'type'] = 'gpot' self.interface[sel_spike, 'type'] = 'spike' # Find the input and output ports: self.in_ports = self.interface.in_ports().to_tuples() self.out_ports = self.interface.out_ports().to_tuples() # Find the graded potential and spiking ports: self.gpot_ports = self.interface.gpot_ports().to_tuples() self.spike_ports = self.interface.spike_ports().to_tuples() self.in_gpot_ports = self.interface.in_ports().gpot_ports().to_tuples() self.in_spike_ports = self.interface.in_ports().spike_ports().to_tuples() self.out_gpot_ports = self.interface.out_ports().gpot_ports().to_tuples() self.out_spike_ports = self.interface.out_ports().spike_ports().to_tuples() # Set up mapper between port identifiers and their associated data: if len(data_gpot) != len(self.gpot_ports): raise ValueError('incompatible gpot port data array length') if len(data_spike) != len(self.spike_ports): raise ValueError('incompatible spike port data array length') self.data = {} self.data['gpot'] = gpuarray.to_gpu(data_gpot) self.data['spike'] = gpuarray.to_gpu(data_spike) self.pm = {} self.pm['gpot'] = GPUPortMapper(sel_gpot, self.data['gpot'], make_copy=False) self.pm['spike'] = GPUPortMapper(sel_spike, self.data['spike'], make_copy=False) # MPI Request object for resolving asynchronous transfers: self.req = MPI.Request()
def connect(self, id_0, id_1, pat, int_0=0, int_1=1, compat_check=True): """ Specify connection between two module instances with a Pattern instance. Parameters ---------- id_0, id_1 : str Identifiers of module instances to connect. pat : Pattern Pattern instance. int_0, int_1 : int Which of the pattern's interfaces to connect to `id_0` and `id_1`, respectively. compat_check : bool Check whether the interfaces of the specified modules are compatible with the specified pattern. This option is provided because compatibility checking can be expensive. Notes ----- Assumes that the constructors of the module types contain a `sel` parameter. """ if not isinstance(pat, Pattern): raise ValueError('pat is not a Pattern instance') if id_0 not in self.rank_to_id.values(): raise ValueError('unrecognized module id %s' % id_0) if id_1 not in self.rank_to_id.values(): raise ValueError('unrecognized module id %s' % id_1) if not (int_0 in pat.interface_ids and int_1 in pat.interface_ids): raise ValueError('unrecognized pattern interface identifiers') self.log_info('connecting modules {0} and {1}'.format(id_0, id_1)) # Check compatibility of the interfaces exposed by the modules and the # pattern; since the manager only contains module classes and not class # instances, we need to create Interface instances from the selectors # associated with the modules in order to test their compatibility: if compat_check: rank_0 = self.rank_to_id.inv[id_0] rank_1 = self.rank_to_id.inv[id_1] self.log_info('checking compatibility of modules {0} and {1} and' ' assigned pattern'.format(id_0, id_1)) mod_int_0 = Interface(self._kwargs[rank_0]['sel']) mod_int_0[self._kwargs[rank_0]['sel']] = 0 mod_int_1 = Interface(self._kwargs[rank_1]['sel']) mod_int_1[self._kwargs[rank_1]['sel']] = 0 mod_int_0[self._kwargs[rank_0]['sel_in'], 'io'] = 'in' mod_int_0[self._kwargs[rank_0]['sel_out'], 'io'] = 'out' mod_int_0[self._kwargs[rank_0]['sel_gpot'], 'type'] = 'gpot' mod_int_0[self._kwargs[rank_0]['sel_spike'], 'type'] = 'spike' mod_int_1[self._kwargs[rank_1]['sel_in'], 'io'] = 'in' mod_int_1[self._kwargs[rank_1]['sel_out'], 'io'] = 'out' mod_int_1[self._kwargs[rank_1]['sel_gpot'], 'type'] = 'gpot' mod_int_1[self._kwargs[rank_1]['sel_spike'], 'type'] = 'spike' if not mod_int_0.is_compatible(0, pat.interface, int_0, True): raise ValueError('module %s interface incompatible ' 'with pattern interface %s' % (id_0, int_0)) if not mod_int_1.is_compatible(0, pat.interface, int_1, True): raise ValueError('module %s interface incompatible ' 'with pattern interface %s' % (id_1, int_1)) # XXX Need to check for fan-in XXX # Store the pattern information in the routing table: self.log_info('updating routing table with pattern') if pat.is_connected(0, 1): self.routing_table[id_0, id_1] = { 'pattern': pat, 'int_0': int_0, 'int_1': int_1 } if pat.is_connected(1, 0): self.routing_table[id_1, id_0] = { 'pattern': pat, 'int_0': int_1, 'int_1': int_0 } self.log_info('connected modules {0} and {1}'.format(id_0, id_1))
def __init__(self, selector, data, columns=['interface', 'io', 'type'], port_data=PORT_DATA, port_ctrl=PORT_CTRL, id=None, debug=False): self.debug = debug # Generate a unique ID if none is specified: if id is None: id = uid() super(BaseModule, self).__init__(port_ctrl, id) # Logging: self.logger = twiggy.log.name('module %s' % self.id) # Data port: if port_data == port_ctrl: raise ValueError('data and control ports must differ') self.port_data = port_data # Initial network connectivity: self.net = 'none' # Create module interface given the specified ports: self.interface = Interface(selector, columns) # Set the interface ID to 0; we assume that a module only has one interface: self.interface[selector, 'interface'] = 0 # Set up mapper between port identifiers and their associated data: assert len(data) == len(self.interface) self.data = data self.pm = PortMapper(self.data, selector) # Patterns connecting this module instance with other modules instances. # Keyed on the IDs of those modules: self.patterns = {} # Each entry in pat_ints is a tuple containing the identifiers of which # of a pattern's identifiers are connected to the current module (first # entry) and the modules to which it is connected (second entry). # Keyed on the IDs of those modules: self.pat_ints = {} # Dict for storing incoming data; each entry (corresponding to each # module that sends input to the current module) is a deque containing # incoming data, which in turn contains transmitted data arrays. Deques # are used here to accommodate situations when multiple data from a # single source arrive: self._in_data = {} # List for storing outgoing data; each entry is a tuple whose first # entry is the source or destination module ID and whose second entry is # the data to transmit: self._out_data = [] # Dictionary containing ports of source modules that # send output to this module. Must be initialized immediately before # an emulation begins running. Keyed on source module ID: self._in_port_dict = {} # Dictionary containing ports of destination modules that # receive input from this module. Must be initialized immediately before # an emulation begins running. Keyed on destination module ID: self._out_port_dict = {} self._out_ids = [] self._in_ids = []