def __init__(s, num_entries, Type):
s.enq = InValRdyIfc(Type)
s.deq = OutValRdyIfc(Type)
s.num_free_entries = OutVPort(mk_bits(clog2(num_entries)))
# Ctrl and Dpath unit instantiation
s.ctrl = NormalQueueRTLCtrl(num_entries)
s.dpath = NormalQueueRTLDpath(num_entries, Type)
# Ctrl unit connections
s.connect(s.ctrl.enq_val, s.enq.val)
s.connect(s.ctrl.enq_rdy, s.enq.rdy)
s.connect(s.ctrl.deq_val, s.deq.val)
s.connect(s.ctrl.deq_rdy, s.deq.rdy)
s.connect(s.ctrl.num_free_entries, s.num_free_entries)
# Dpath unit connections
s.connect(s.dpath.enq_bits, s.enq.msg)
s.connect(s.dpath.deq_bits, s.deq.msg)
# Control Signal connections (ctrl -> dpath)
s.connect(s.dpath.wen, s.ctrl.wen)
s.connect(s.dpath.waddr, s.ctrl.waddr)
s.connect(s.dpath.raddr, s.ctrl.raddr)
def __init__(s, Type):
s.enq = InValRdyIfc(Type)
s.deq = OutValRdyIfc(Type)
s.buf = RegEn(Type)(out=s.deq.msg, in_=s.enq.msg)
s.next_full = Wire(int if Type is int else Bits1)
s.full = Wire(int if Type is int else Bits1)
s.connect(s.full, s.deq.val)
@s.update_on_edge
def up_full():
s.full = s.next_full
if Type is int:
@s.update
def up_pipeq_set_enq_rdy():
s.enq.rdy = (not s.full) | s.deq.rdy
@s.update
def up_pipeq_full():
s.buf.en = s.enq.val & s.enq.rdy
s.next_full = s.enq.val | (s.full & (not s.deq.rdy))
else:
@s.update
def up_pipeq_set_enq_rdy():
s.enq.rdy = ~s.full | s.deq.rdy
@s.update
def up_pipeq_full():
s.buf.en = s.enq.val & s.enq.rdy
s.next_full = s.enq.val | (s.full & ~s.deq.rdy)
def __init__(s, nbits=32):
assert nbits % 2 == 0
s.req = InValRdyIfc(mk_bits(nbits * 2))
s.resp = OutValRdyIfc(mk_bits(nbits * 2))
s.dpath = IntDivRem4Dpath(nbits)(
req_msg=s.req.msg,
resp_msg=s.resp.msg,
)
s.ctrl = IntDivRem4Ctrl(nbits)(
req_val=s.req.val,
req_rdy=s.req.rdy,
resp_val=s.resp.val,
resp_rdy=s.resp.rdy,
# Status signals
sub_negative1=s.dpath.sub_negative1,
sub_negative2=s.dpath.sub_negative2,
# Control signals
quotient_mux_sel=s.dpath.quotient_mux_sel,
quotient_reg_en=s.dpath.quotient_reg_en,
remainder_mux_sel=s.dpath.remainder_mux_sel,
remainder_reg_en=s.dpath.remainder_reg_en,
divisor_mux_sel=s.dpath.divisor_mux_sel,
)
def __init__(s, Type):
s.enq = InValRdyIfc(Type)
s.deq = OutValRdyIfc(Type)
s.buf = RegEn(Type)(in_=s.enq.msg)
s.next_full = Wire(int if Type is int else Bits1)
s.full = Wire(int if Type is int else Bits1)
s.byp_mux = Mux(Type, 2)(
out=s.deq.msg,
in_={
0: s.enq.msg,
1: s.buf.out,
},
sel=s.full, # full -- buf.out, empty -- bypass
)
@s.update_on_edge
def up_full():
s.full = s.next_full
if Type is int:
@s.update
def up_bypq_set_enq_rdy():
s.enq.rdy = not s.full
@s.update
def up_bypq_internal():
s.buf.en = (not s.deq.rdy) & (s.enq.val & s.enq.rdy)
s.next_full = (not s.deq.rdy) & s.deq.val
else:
@s.update
def up_bypq_set_enq_rdy():
s.enq.rdy = ~s.full
@s.update
def up_bypq_internal():
s.buf.en = (~s.deq.rdy) & (s.enq.val & s.enq.rdy)
s.next_full = (~s.deq.rdy) & s.deq.val
# this enables the sender to make enq.val depend on enq.rdy
@s.update
def up_bypq_set_deq_val():
s.deq.val = s.full | s.enq.val
def __init__( s, nports = 1, req_types = [ MemReqMsg(8,32,32) ], \
resp_types = [ MemRespMsg(8,32) ],
mem_nbytes=1<<20 ):
s.mem = TestMemory(mem_nbytes)
s.reqs = [InValRdyIfc(req_types[i]) for i in xrange(nports)]
s.resps = [OutValRdyIfc(resp_types[i]) for i in xrange(nports)]
s.resp_qs = [PipeQueue1RTL(resp_types[i]) for i in xrange(nports)]
for i in xrange(nports):
s.connect(s.resps[i], s.resp_qs[i].deq)
s.req_types = req_types
s.resp_types = resp_types
s.nports = nports
@s.update
def up_set_rdy():
for i in xrange(nports):
s.reqs[i].rdy = s.resp_qs[i].enq.rdy
@s.update
def up_process_memreq():
for i in xrange(nports):
s.resp_qs[i].enq.val = Bits1(0)
if s.reqs[i].val & s.resp_qs[i].enq.rdy:
req = s.reqs[i].msg
len = req.len if req.len else (
s.reqs[i].msg.data.nbits >> 3)
if req.type_ == MemReqMsg.TYPE_READ:
resp = s.resp_types[i].mk_rd(req.opaque, len,
s.mem.read(req.addr, len))
elif req.type_ == MemReqMsg.TYPE_WRITE:
s.mem.write(req.addr, len, req.data)
resp = s.resp_types[i].mk_wr(req.opaque)
else: # AMOS
resp = s.resp_types[i].mk_msg( req.type_, req.opaque, 0, len, \
s.mem.amo( req.type_, req.addr, len, req.data ))
s.resp_qs[i].enq.val = Bits1(1)
s.resp_qs[i].enq.msg = resp
def __init__(s, Type, msgs):
assert type(msgs) == list, "TestSink only accepts a list of outputs!"
s.msgs = msgs
s.sink_msgs = deque(s.msgs)
s.in_ = InValRdyIfc(Type)
@s.update_on_edge
def up_sink():
if s.reset:
s.in_.rdy = Bits1(0)
s.sink_msgs = deque(s.msgs)
else:
s.in_.rdy = Bits1(len(s.sink_msgs) > 0)
if s.in_.val and s.in_.rdy:
ref = s.sink_msgs.popleft()
ans = s.in_.msg
assert ref == ans, "Expect %s, get %s instead" % (ref, ans)
def __init__(s, Type, msgs):
assert type(msgs) == list, "TestSink only accepts a list of outputs!"
s.msgs = deque(msgs)
s.recv = deque()
s.in_ = InValRdyIfc(Type)
@s.update_on_edge
def up_sink():
s.in_.rdy = len(s.msgs) > 0
if s.in_.val and s.in_.rdy:
ans = s.in_.msg
if ans not in s.msgs:
if ans in s.recv:
raise AssertionError("Message %s arrived twice!" % ans)
else:
raise AssertionError(
"Message %s not found in Test Sink!" % ans)
s.msgs.remove(ans)
s.recv.append(ans)