def __init__(s):
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.req_msg_a = InPort(16)
s.req_msg_b = InPort(16)
s.resp_msg = OutPort(16)
# Control signals (ctrl -> dpath)
s.a_mux_sel = InPort(A_MUX_SEL_NBITS)
s.a_reg_en = InPort(1)
s.b_mux_sel = InPort(B_MUX_SEL_NBITS)
s.b_reg_en = InPort(1)
# Status signals (dpath -> ctrl)
s.is_b_zero = OutPort(1)
s.is_a_lt_b = OutPort(1)
#---------------------------------------------------------------------
# Structural composition
#---------------------------------------------------------------------
# A mux
s.sub_out = Wire(16)
s.b_reg_out = Wire(16)
s.a_mux = m = Mux(16, 3)
s.connect_dict({
m.sel: s.a_mux_sel,
m.in_[A_MUX_SEL_IN]: s.req_msg_a,
m.in_[A_MUX_SEL_SUB]: s.sub_out,
m.in_[A_MUX_SEL_B]: s.b_reg_out,
})
# A register
s.a_reg = m = RegEn(16)
s.connect_dict({
m.en: s.a_reg_en,
m.in_: s.a_mux.out,
})
# B mux
s.b_mux = m = Mux(16, 2)
s.connect_dict({
m.sel: s.b_mux_sel,
m.in_[B_MUX_SEL_A]: s.a_reg.out,
m.in_[B_MUX_SEL_IN]: s.req_msg_b,
})
# B register
s.b_reg = m = RegEn(16)
s.connect_dict({
m.en: s.b_reg_en,
m.in_: s.b_mux.out,
m.out: s.b_reg_out,
})
# Zero compare
s.b_zero = m = ZeroComparator(16)
s.connect_dict({
m.in_: s.b_reg.out,
m.out: s.is_b_zero,
})
# Less-than comparator
s.a_lt_b = m = LtComparator(16)
s.connect_dict({
m.in0: s.a_reg.out,
m.in1: s.b_reg.out,
m.out: s.is_a_lt_b
})
# Subtractor
s.sub = m = Subtractor(16)
s.connect_dict({
m.in0: s.a_reg.out,
m.in1: s.b_reg.out,
m.out: s.sub_out,
})
# connect to output port
s.connect(s.sub.out, s.resp_msg)
def __init__(s, k=3):
SUM_DATA_SIZE = int(math.ceil(math.log(50 * k, 2)))
s.req_msg_data = InPort(RE_DATA_SIZE)
s.resp_msg_digit = OutPort(4)
# ctrl->dpath
s.knn_wr_data_mux_sel = InPort(1)
s.knn_wr_addr = InPort(int(math.ceil(math.log(k * DIGIT,
2)))) # max 30
s.knn_rd_addr = InPort(int(math.ceil(math.log(k * DIGIT,
2)))) # max 30
s.knn_wr_en = InPort(1)
s.vote_wr_data_mux_sel = InPort(1)
s.vote_wr_addr = InPort(int(math.ceil(math.log(DIGIT, 2)))) # max 10
s.vote_rd_addr = InPort(int(math.ceil(math.log(DIGIT, 2)))) # max 10
s.vote_wr_en = InPort(1)
s.FindMax_req_val = InPort(1)
s.FindMax_resp_rdy = InPort(1)
s.FindMin_req_val = InPort(1)
s.FindMin_resp_rdy = InPort(1)
s.msg_data_reg_en = InPort(1)
s.msg_idx_reg_en = InPort(1)
# dpath->ctrl
s.FindMax_req_rdy = OutPort(1)
s.FindMax_resp_val = OutPort(1)
s.FindMax_resp_idx = OutPort(int(math.ceil(math.log(k, 2)))) # max 3
s.FindMin_req_rdy = OutPort(1)
s.FindMin_resp_val = OutPort(1)
s.isSmaller = OutPort(1)
# internal wires
s.knn_rd_data = Wire(Bits(RE_DATA_SIZE))
s.knn_wr_data = Wire(Bits(RE_DATA_SIZE))
s.subtractor_out = Wire(Bits(SUM_DATA_SIZE))
s.adder_out = Wire(Bits(SUM_DATA_SIZE))
s.vote_rd_data = Wire(Bits(SUM_DATA_SIZE))
s.vote_wr_data = Wire(Bits(SUM_DATA_SIZE))
s.FindMax_req_data = Wire(Bits(RE_DATA_SIZE))
s.FindMax_resp_data = Wire(Bits(RE_DATA_SIZE))
s.FindMin_req_data = Wire(Bits(SUM_DATA_SIZE))
s.FindMin_resp_data = Wire(Bits(SUM_DATA_SIZE))
s.FindMin_resp_idx = Wire(Bits(int(math.ceil(math.log(DIGIT,
2))))) # max 10
# Req msg data Register
s.req_msg_data_q = Wire(Bits(RE_DATA_SIZE))
s.req_msg_data_reg = m = RegEnRst(RE_DATA_SIZE)
s.connect_dict({
m.en: s.msg_data_reg_en,
m.in_: s.req_msg_data,
m.out: s.req_msg_data_q
})
# knn_wr_data Mux
s.knn_wr_data_mux = m = Mux(RE_DATA_SIZE, 2)
s.connect_dict({
m.sel: s.knn_wr_data_mux_sel,
m.in_[0]: 50,
m.in_[1]: s.req_msg_data_q,
m.out: s.knn_wr_data
})
# register file knn_table
s.knn_table = m = RegisterFile(dtype=Bits(RE_DATA_SIZE),
nregs=k * DIGIT,
rd_ports=1,
wr_ports=1,
const_zero=False)
s.connect_dict({
m.rd_addr[0]: s.knn_rd_addr,
m.rd_data[0]: s.knn_rd_data,
m.wr_addr: s.knn_wr_addr,
m.wr_data: s.knn_wr_data,
m.wr_en: s.knn_wr_en
})
# vote_wr_data Mux
s.vote_wr_data_mux = m = Mux(SUM_DATA_SIZE, 2)
s.connect_dict({
m.sel: s.vote_wr_data_mux_sel,
m.in_[0]: 50 * k,
m.in_[1]: s.adder_out,
m.out: s.vote_wr_data
})
# register file knn_vote
s.knn_vote = m = RegisterFile(dtype=Bits(SUM_DATA_SIZE),
nregs=DIGIT,
rd_ports=1,
wr_ports=1,
const_zero=False)
s.connect_dict({
m.rd_addr[0]: s.vote_rd_addr,
m.rd_data[0]: s.vote_rd_data,
m.wr_addr: s.vote_wr_addr,
m.wr_data: s.vote_wr_data,
m.wr_en: s.vote_wr_en
})
# Find max value of knn_table for a given digit
s.connect_wire(s.knn_rd_data, s.FindMax_req_data)
s.findmax = m = FindMaxPRTL(RE_DATA_SIZE, k)
s.connect_dict({
m.req.val: s.FindMax_req_val,
m.req.rdy: s.FindMax_req_rdy,
m.req.msg.data: s.FindMax_req_data,
m.resp.val: s.FindMax_resp_val,
m.resp.rdy: s.FindMax_resp_rdy,
m.resp.msg.data: s.FindMax_resp_data,
m.resp.msg.idx: s.FindMax_resp_idx
})
# Less than comparator
s.knn_LtComparator = m = LtComparator(RE_DATA_SIZE)
s.connect_dict({
m.in0: s.req_msg_data_q,
m.in1: s.FindMax_resp_data,
m.out: s.isSmaller
})
# Zero extender
s.FindMax_resp_data_zext = Wire(Bits(SUM_DATA_SIZE))
s.FindMax_resp_data_zexter = m = ZeroExtender(RE_DATA_SIZE,
SUM_DATA_SIZE)
s.connect_dict({
m.in_: s.FindMax_resp_data,
m.out: s.FindMax_resp_data_zext,
})
# Subtractor
s.subtractor = m = Subtractor(SUM_DATA_SIZE)
s.connect_dict({
m.in0: s.vote_rd_data,
m.in1: s.FindMax_resp_data_zext,
m.out: s.subtractor_out
})
# Zero extender
s.req_msg_data_zext = Wire(Bits(SUM_DATA_SIZE))
s.req_msg_data_zexter = m = ZeroExtender(RE_DATA_SIZE, SUM_DATA_SIZE)
s.connect_dict({
m.in_: s.req_msg_data_q,
m.out: s.req_msg_data_zext,
})
# Adder
s.adder = m = Adder(SUM_DATA_SIZE)
s.connect_dict({
m.in0: s.subtractor_out,
m.in1: s.req_msg_data_zext,
m.cin: 0,
m.out: s.adder_out
})
# Find min value of knn_vote, return digit
s.connect_wire(s.vote_rd_data, s.FindMin_req_data)
s.findmin = m = FindMinPRTL(SUM_DATA_SIZE, DIGIT)
s.connect_dict({
m.req.val: s.FindMin_req_val,
m.req.rdy: s.FindMin_req_rdy,
m.req.msg.data: s.FindMin_req_data,
m.resp.val: s.FindMin_resp_val,
m.resp.rdy: s.FindMin_resp_rdy,
m.resp.msg.data: s.FindMin_resp_data,
m.resp.msg.digit: s.FindMin_resp_idx
})
# Resp idx Register
s.resp_msg_idx_q = Wire(Bits(int(math.ceil(math.log(DIGIT, 2)))))
s.req_msg_idx_reg = m = RegEnRst(int(math.ceil(math.log(DIGIT, 2))))
s.connect_dict({
m.en: s.msg_idx_reg_en,
m.in_: s.FindMin_resp_idx,
m.out: s.resp_msg_idx_q
})
# connect output idx
s.connect(s.resp_msg_idx_q, s.resp_msg_digit)
def __init__(s):
#==================================================================
# Interfaces
#==================================================================
s.a = InPort(32)
# s.look_ahead_cnt = InPort ( 6 )
s.shamt = OutPort(6)
#==================================================================
# Structure
#==================================================================
# Substractor (s.a - 1)
s.sub = m = Subtractor(32)
s.sub_out = Wire(32)
s.connect_pairs(
m.in0,
s.a,
m.in1,
1,
m.out,
s.sub_out,
)
# Right shifter
s.rshift = m = RightLogicalShifter(32)
s.xor_out = Wire(32)
s.xor_not_out = Wire(32)
s.rshift_out = Wire(32)
s.and_out = Wire(32)
s.connect_pairs(
m.in_,
s.xor_not_out,
m.shamt,
1,
m.out,
s.rshift_out,
)
# Encoder
s.encoder = m = Encoder()
s.encoder_out = Wire(6)
s.connect_pairs(
m.in_,
s.and_out,
m.out,
s.encoder_out,
)
# MUX
s.mux = m = Mux(6, 2)
s.mux_sel = Wire(MUX_SEL_NBITS)
s.connect_pairs(
m.sel,
s.mux_sel,
m.in_[MUX_SEL_ENCODER],
s.encoder_out,
m.in_[MUX_SEL_SKIP],
32,
# m.in_[ MUX_SEL_SKIP ], s.look_ahead_cnt,
m.out,
s.shamt,
)
#==================================================================
# Combinational Logic
#==================================================================
@s.combinational
def xor_block():
s.xor_out.value = s.a ^ s.sub_out
s.xor_not_out.value = ~(s.a ^ s.sub_out)
@s.combinational
def and_block():
s.and_out.value = s.rshift_out & s.xor_out
@s.combinational
def mux_sel_block():
s.mux_sel.value = s.encoder_out[0] | s.encoder_out[1] | \
s.encoder_out[2] | s.encoder_out[3] | \
s.encoder_out[4] | s.encoder_out[5]
def __init__(s, nbits):
nbitsx2 = nbits * 2
dtype = mk_bits(nbits)
dtypex2 = mk_bits(nbitsx2)
s.req_msg = InVPort(dtypex2)
s.resp_msg = OutVPort(dtypex2)
# Status signals
s.sub_negative1 = OutVPort(Bits1)
s.sub_negative2 = OutVPort(Bits1)
# Control signals
s.quotient_mux_sel = InVPort(Bits1)
s.quotient_reg_en = InVPort(Bits1)
s.remainder_mux_sel = InVPort(Bits2)
s.remainder_reg_en = InVPort(Bits1)
s.divisor_mux_sel = InVPort(Bits1)
# Dpath components
s.remainder_mux = Mux(dtypex2, 3)(sel=s.remainder_mux_sel)
@s.update
def up_remainder_mux_in0():
s.remainder_mux.in_[R_MUX_SEL_IN] = dtypex2()
s.remainder_mux.in_[R_MUX_SEL_IN][0:nbits] = s.req_msg[0:nbits]
s.remainder_reg = RegEn(dtypex2)(
in_=s.remainder_mux.out,
en=s.remainder_reg_en,
)
# lower bits of resp_msg save the remainder
s.connect(s.resp_msg[0:nbits], s.remainder_reg.out[0:nbits])
s.divisor_mux = Mux(dtypex2, 2)(sel=s.divisor_mux_sel)
@s.update
def up_divisor_mux_in0():
s.divisor_mux.in_[D_MUX_SEL_IN] = dtypex2()
s.divisor_mux.in_[D_MUX_SEL_IN][nbits - 1:nbitsx2 -
1] = s.req_msg[nbits:nbitsx2]
s.divisor_reg = Reg(dtypex2)(in_=s.divisor_mux.out)
s.quotient_mux = Mux(dtype, 2)(sel=s.quotient_mux_sel)
s.connect(s.quotient_mux.in_[Q_MUX_SEL_0], 0)
s.quotient_reg = RegEn(dtype)(
in_=s.quotient_mux.out,
en=s.quotient_reg_en,
# higher bits of resp_msg save the quotient
out=s.resp_msg[nbits:nbitsx2],
)
# shamt should be 2 bits!
s.quotient_lsh = LShifter(dtype, 2)(in_=s.quotient_reg.out)
s.connect(s.quotient_lsh.shamt, 2)
s.inc = Wire(Bits2)
s.connect(s.sub_negative1, s.inc[1])
s.connect(s.sub_negative2, s.inc[0])
@s.update
def up_quotient_inc():
s.quotient_mux.in_[Q_MUX_SEL_LSH] = s.quotient_lsh.out + ~s.inc
# stage 1/2
s.sub1 = Subtractor(dtypex2)(
in0=s.remainder_reg.out,
in1=s.divisor_reg.out,
out=s.remainder_mux.in_[R_MUX_SEL_SUB1],
)
s.connect(s.sub_negative1, s.sub1.out[nbitsx2 - 1])
s.remainder_mid_mux = Mux(dtypex2, 2)(
in_={
0: s.sub1.out,
1: s.remainder_reg.out,
},
sel=s.sub_negative1,
)
s.divisor_rsh1 = RShifter(dtypex2, 1)(in_=s.divisor_reg.out, )
s.connect(s.divisor_rsh1.shamt, 1)
# stage 2/2
s.sub2 = Subtractor(dtypex2)(
in0=s.remainder_mid_mux.out,
in1=s.divisor_rsh1.out,
out=s.remainder_mux.in_[R_MUX_SEL_SUB2],
)
s.connect(s.sub_negative2, s.sub2.out[nbitsx2 - 1])
s.divisor_rsh2 = RShifter(dtypex2, 1)(
in_=s.divisor_rsh1.out,
out=s.divisor_mux.in_[D_MUX_SEL_RSH],
)
s.connect(s.divisor_rsh2.shamt, 1)