def test_force(self):
""" Just instanciate a port """
aport = Port(None, name="simpleport")
aport.force = "gnd"
aport.force = "vcc"
aport.force = "undef"
self.assertEqual(aport.force, "undef")
with self.assertRaises(PodError):
aport.force = "pouet"
def generateXML(self,masterinterface):
""" Generate intercon code
"""
masterinstance = masterinterface.getParent()
# set name and description
self.setName(str(masterinstance.getInstanceName()) \
+ "_" \
+ str(masterinterface.getName()))
self.setInstanceName(str(masterinstance.getInstanceName())\
+ "_"\
+str(masterinterface.getName())\
+ "_intercon")
self.setDescription("Connect slaves to "\
+ masterinterface.getName()\
+ " from "\
+ masterinstance.getInstanceName())
# Save to make directories
self.saveInstance()
#####
# Create interface for each component connected on intercon
# for slaves and master:
slaveslist = masterinterface.getSlavesList()
interfaceslist = [slave.getInterface() for slave in slaveslist]
interfaceslist.append(masterinterface)
# For each slave and master interface, create interface in intercon
for interface in interfaceslist:
instance = interface.getParent()
#######
# bus (wishbone,...)
bus = Interface(self,
name=instance.getInstanceName()\
+"_"+interface.getName())
bus.setClass("intercon")
# Adding bus interface on intercon
self.addInterface(bus)
#Creating port with invert direction value
for port in interface.getPortsList():
newport = Port(bus,
name=instance.getInstanceName()\
+"_"+port.getName())
newport.setDir(self.invertDir(port.getDir()))
newport.setSize(port.getSize())
# adding port on bus interface
bus.addPort(newport)
#connect port new port on instance interface
port.connectAllPin(newport)
bus.setClass("intercon")
self.setNum("0")
def generate_xml(self, masterinterface):
""" Generate intercon code
"""
masterinstance = masterinterface.parent
# set name and description
self.name = str(masterinstance.instancename) +\
"_" + str(masterinterface.name)
self.instancename = masterinstance.instancename +\
"_" + masterinterface.name +\
"_intercon"
self.description = "Connect slaves to " + masterinterface.name +\
" from " + masterinstance.instancename
# Save to make directories
self.save()
# Create interface for each component connected on intercon
# for slaves and master:
slaveslist = masterinterface.slaves
interfaceslist = [slave.get_interface() for slave in slaveslist]
interfaceslist.append(masterinterface)
# For each slave and master interface, create interface in intercon
for interface in interfaceslist:
instance = interface.parent
# bus (wishbone,...)
bus = Interface(self,
name=instance.instancename +
"_" + interface.name)
bus.interface_class = "intercon"
# Adding bus interface on intercon
self.add_interface(bus)
# Creating port with invert direction value
for port in interface.ports:
newport = Port(bus,
name=instance.instancename +
"_" + port.name)
newport.direction = self.inv_direction(port.direction)
newport.size = port.size
# adding port on bus interface
bus.add_port(newport)
# connect port new port on instance interface
port.connect_all_pins(newport)
bus.interface_class = "intercon"
self.num = "0"
def getPortsList(self):
""" Parse HDL file and return a list of ports"""
if not self.isTop():
raise Error("Only top HDL file can be parsed")
if self.parser == None:
Et = EntityParser()
self.parser = Et.factory(self.getFilePath())
parsedportlist = self.parser.parsePort()
portlist = []
for parsedport in parsedportlist:
port = Port(self,name=parsedport["name"])
port.setDir(parsedport["direction"])
port.setSize(str(parsedport["size"]))
port.setDescription(parsedport["description"])
portlist.append(port)
return portlist
def __init__(self, parent, **keys):
""" Create interface object
if node is a node or name.
__init__(self,parent,name)
__init__(self,parent,node)
__init__(self,parent,nodestring)
"""
self._parent = parent
if "name" in keys:
WrapperXml.__init__(self, nodename="interface")
self.name = keys["name"]
elif "node" in keys:
WrapperXml.__init__(self, node=keys["node"])
elif "wxml" in keys:
WrapperXml.__init__(self, nodestring=keys["wxml"])
else:
raise PodError("Keys unknown in Interface", 0)
self._registerslist = []
self.portslist = []
self._slaveslist = []
self._bus = None
if self.interface_class == "master":
self.alloc_mem = AllocMem(self)
if self.interface_class == "slave":
self.interfacemaster = None
if self.get_node("slaves") is not None:
for element in self.get_subnodes("slaves", "slave"):
self._slaveslist.append(Slave(self, node=element))
if self.get_node("registers") is not None:
for element in self.get_subnodes("registers", "register"):
self._registerslist.append(Register(self, node=element))
if self.get_node("ports") is not None:
for node in self.get_subnodes("ports", "port"):
self.portslist.append(Port(self, node=node))
# set bus
if self.bus_name is not None:
self.bus = self.bus_name
def test_initport(self):
""" Just instanciate a port """
aport = Port(None, name="simpleport")