def __init__(self, name, mapping, parent=None):
portlist = dict([('OUT', gate.OUT), ('I0', gate.IN), ('I1', gate.IN),
('I2', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
for i in ('n0', 'n1', 'n2'):
self.netlist[i] = net.net(i, parent=self)
# Add depln mode pullups
self.netlist['n0'].pullup_str = 100
self.port['OUT'].netconn.pullup_str = 100
self.gatelist.extend([
NMOS("NMOS_0_u", [
self.netlist['n0'], self.netlist['n1'], self.port['I0'].netconn
], self),
NMOS("NMOS_1_u", [
self.netlist['n1'], self.netlist['n2'], self.port['I1'].netconn
], self),
NMOS("NMOS_2_u", [
self.netlist['n2'], self.netlist['vss'],
self.port['I2'].netconn
], self),
NMOS("NMOS_3_u", [
self.port['OUT'].netconn, self.netlist['vss'],
self.netlist['n0']
], self),
])
def __init__(self, name, mapping, parent=None):
portlist = dict([('Q', gate.OUT), ('D', gate.IN), ('RSTB', gate.IN),
('PHI', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
for i in ('phib', 'rst', 'n0'):
self.netlist[i] = net.net(i, parent=self, pullup_str=100)
self.netlist['n1'] = net.net('n1', parent=self, charge_storage=True)
self.netlist['n2'] = net.net('n2', parent=self, charge_storage=True)
self.port['Q'].netconn.pullup_str += 100
self.gatelist.extend([
# Inverters for the clock and reset signals
NMOS("NMOS_0_u", [
self.netlist['phib'], self.netlist['vss'],
self.port['PHI'].netconn
], self),
NMOS("NMOS_1_u", [
self.netlist['rst'], self.netlist['vss'],
self.port['RSTB'].netconn
], self),
# 2 half latches
NMOS("NMOS_2_u",
[self.netlist['n0'], self.netlist['vss'], self.netlist['n1']],
self),
NMOS("NMOS_3_u", [
self.netlist['n1'], self.port['D'].netconn,
self.netlist['phib']
], self),
NMOS("NMOS_4_u", [
self.port['Q'].netconn, self.netlist['vss'], self.netlist['n2']
], self),
NMOS("NMOS_5_u", [
self.netlist['n2'], self.netlist['n0'],
self.port['PHI'].netconn
], self),
# Reset first and second latches in opposite directions - must be strong drivers to win contention vs pass gates
NMOS(
"NMOS_6_u",
[self.netlist['n1'], self.netlist['vss'], self.netlist['rst']],
self),
NMOS(
"NMOS_7_u",
[self.netlist['n2'], self.netlist['vdd'], self.netlist['rst']],
self),
])
def __init__(self, name, mapping, parent=None):
portlist = dict([('OUT', gate.OUT), ('IN', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
# Add depln mode pullups
self.netlist['n0'] = net.net('n0', pullup_str=100, parent=self)
self.port['OUT'].netconn.pullup_str = 100
self.gatelist.extend([
NMOS("NMOS_0_u", [
self.port['OUT'].netconn, self.netlist['vss'],
self.netlist['n0']
], self),
NMOS("NMOS_1_u", [
self.netlist['n0'], self.netlist['vss'],
self.port['IN'].netconn
], self),
])
def __init__(self, name, mapping, parent=None):
portlist = dict([('OUT', gate.OUT), ('I0', gate.IN), ('I1', gate.IN),
('I2', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
# Add depln mode pullups
self.port['OUT'].netconn.pullup_str = 100
self.netlist['n0'] = net.net('n0', parent=self)
self.netlist['n1'] = net.net('n1', parent=self)
self.gatelist.extend([
NMOS("NMOS_0_u", [
self.port['OUT'].netconn, self.netlist['n0'],
self.port['I0'].netconn
], self),
NMOS("NMOS_1_u", [
self.port['OUT'].netconn, self.netlist['n1'],
self.port['I1'].netconn
], self),
NMOS("NMOS_2_u", [
self.netlist['n0'], self.netlist['vss'],
self.port['I1'].netconn
], self),
NMOS("NMOS_3_u", [
self.netlist['n1'], self.netlist['vss'],
self.port['I0'].netconn
], self),
# This has to be a bidir gate to work
NMOS("NMOS_4_u", [
self.netlist['n1'], self.netlist['n0'], self.port['I2'].netconn
], self),
])
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['write']))
self.netlist.update(
gate.wire(['data0_in', 'n10', 'n20', 'bit0', 'bit0_b', 'word0']))
self.netlist.update(
gate.wire(['data1_in', 'n11', 'n21', 'bit1', 'bit1_b', 'word1']))
self.netlist.update(
gate.wire(['data2_in', 'n12', 'n22', 'bit2', 'bit2_b', 'word2']))
self.netlist.update(
gate.wire(['data3_in', 'n13', 'n23', 'bit3', 'bit3_b', 'word3']))
for j in range(0, 4):
for i in range(0, 4):
self.netlist.update(
gate.wire([
'word%d%d' % (i, j),
'q%d%d' % (i, j),
'q%d%d_b' % (i, j)
]))
self.netlist['q%d%d' % (i, j)].pullup_str = net.DEPL_STR
self.netlist['q%d%d_b' % (i, j)].pullup_str = net.DEPL_STR
self.netlist['n1%d' % j].pullup_str = net.DEPL_STR
self.netlist['n2%d' % j].pullup_str = net.DEPL_STR
self.gatelist = []
for j in range(0, 4):
for i in range(0, 4):
self.gatelist.extend([
NMOS("ram%d%d_0_u" % (j, i), [
self.netlist['q%d%d' % (j, i)], self.netlist['vss'],
self.netlist['q%d%d_b' % (j, i)]
],
parent=self),
NMOS("ram%d%d_1_u" % (j, i), [
self.netlist['q%d%d_b' % (j, i)], self.netlist['vss'],
self.netlist['q%d%d' % (j, i)]
],
parent=self),
NMOS("ram%d%d_2_u" % (j, i), [
self.netlist['bit%d' % i], self.netlist['q%d%d' %
(j, i)],
self.netlist['word%d' % j]
],
parent=self),
NMOS("ram%d%d_3_u" % (i, j), [
self.netlist['bit%d_b' % i], self.netlist['q%d%d_b' %
(j, i)],
self.netlist['word%d' % j]
],
parent=self)
])
self.gatelist.extend([
NMOS("ctrl_0%d_u" % j, [
self.netlist['bit%d' % j], self.netlist['n2%d' % j],
self.netlist['write']
], self),
NMOS("ctrl_1%d_u" % j, [
self.netlist['bit%d_b' % j], self.netlist['n1%d' % j],
self.netlist['write']
], self),
NMOS("ctrl_2%d_u" % j, [
self.netlist['n1%d' % j], self.netlist['vss'],
self.netlist['data%d_in' % j]
], self),
NMOS("ctrl_4%d_u" % j, [
self.netlist['n2%d' % j], self.netlist['vss'],
self.netlist['n1%d' % j]
], self)
])
vector_string = '''
PI data3_in
PI data2_in
PI data1_in
PI data0_in
PI write
PI word3
PI word2
PI word1
PI word0
PO q33
PO q32
PO q31
PO q30
PO q23
PO q22
PO q21
PO q20
PO q13
PO q12
PO q11
PO q10
PO q03
PO q02
PO q01
PO q00
PO bit3
PO bit2
PO bit1
PO bit0
PO bit3_b
PO bit2_b
PO bit1_b
PO bit0_b
# dddd
# aaaa
# tttt w wwww bbbb
# aaaa r oooo iiii
# 1010 bbbb tttt
# ____ i rrrr qqqq qqqq qqqq qqqq iiii 3210
# iiii t dddd 3333 2222 1111 0000 tttt ____
# nnnn e 3210 3210 3210 3210 3210 3210 bbbb
# ----------------------------------------------
0000 0 0000 XXXX XXXX XXXX XXXX XXXX XXXX
0000 1 0001 XXXX XXXX XXXX LLLL XXXX XXXX
0000 1 0010 XXXX XXXX LLLL LLLL XXXX XXXX
0000 1 0100 XXXX LLLL LLLL LLLL XXXX XXXX
0000 1 1000 LLLL LLLL LLLL LLLL XXXX XXXX
0000 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 0 0001 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 0010 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 0100 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 1000 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 1 0001 LLLL LLLL LLLL HHHH XXXX XXXX
1111 1 0010 LLLL LLLL HHHH HHHH XXXX XXXX
1111 1 0100 LLLL HHHH HHHH HHHH XXXX XXXX
1111 1 1000 HHHH HHHH HHHH HHHH XXXX XXXX
1111 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0001 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 0010 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 0100 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 1000 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0001 HHHH HHHH HHHH LLLL XXXX XXXX
0000 0 0000 HHHH HHHH HHHH LLLL XXXX XXXX
0000 0 0100 HHHH LLLL HHHH LLLL XXXX XXXX
0000 0 0000 HHHH LLLL HHHH LLLL XXXX XXXX
1111 0 0000 HHHH LLLL HHHH LLLL XXXX XXXX
1111 0 0001 HHHH LLLL HHHH LLLL LLLL HHHH
1111 0 0010 HHHH LLLL HHHH LLLL HHHH LLLL
1111 0 0100 HHHH LLLL HHHH LLLL LLLL HHHH
1111 0 1000 HHHH LLLL HHHH LLLL HHHH LLLL
1111 0 0000 HHHH LLLL HHHH LLLL XXXX XXXX
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'in0', 'in1', 'in2', 'in3', 'in4', 'in5', 'n0', 'n1', 'n2',
'n3', 'out'
]))
self.netlist['out'].pullup_str = net.DEPL_STR
self.netlist['n0'].pullup_str = net.DEPL_STR
self.netlist['n1'].pullup_str = net.DEPL_STR
self.netlist['n2'].charge_storage = True
self.netlist['n3'].charge_storage = True
self.gatelist = [
NMOS(
"nmos_0_u",
[self.netlist['n0'], self.netlist['vss'], self.netlist['in0']],
self),
NMOS(
"nmos_1_u",
[self.netlist['n1'], self.netlist['vss'], self.netlist['in1']],
self),
NMOS(
"nmos_2_u",
[self.netlist['n2'], self.netlist['vss'], self.netlist['in2']],
self),
NMOS("nmos_3_u",
[self.netlist['n0'], self.netlist['n2'], self.netlist['in3']],
self),
NMOS("nmos_4_u",
[self.netlist['n1'], self.netlist['n2'], self.netlist['in4']],
self),
UNMOS(
"unmos_5_u",
[self.netlist['n3'], self.netlist['n2'], self.netlist['in5']],
self),
NMOS(
"nmos_6_u",
[self.netlist['out'], self.netlist['vss'], self.netlist['n3']],
self),
]
vector_string = '''
PI in0
PI in1
PI in2
PI in3
PI in4
PI in5
PO n2
PO out
# iiiiii o
# nnnnnn n u
# 012345 2 t
# -------------
111111 L H
000000 L H
000100 H H
000001 H L
000000 H L
101010 L L
010101 H L
000110 H L
000101 H L
101000 L L
000001 L H
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'cclk', 'n821', 'n826', 'n318', 'n1062', 'n1315', 'n705',
'out', 'abh0'
]))
self.netlist['n1315'].pullup_str = net.DEPL_STR
self.netlist['abh0'].pullup_str = net.DEPL_STR
self.netlist['n1062'].charge_storage = True
self.gatelist = [
NMOS("nmos_0_u", [
self.netlist['out'], self.netlist['vdd'], self.netlist['n826']
], self),
NMOS("nmos_1_u", [
self.netlist['out'], self.netlist['vss'], self.netlist['n318']
], self),
NMOS("nmos_2_u", [
self.netlist['n318'], self.netlist['vdd'],
self.netlist['n1315']
], self),
NMOS("nmos_3_u", [
self.netlist['n318'], self.netlist['vss'], self.netlist['abh0']
], self),
NMOS("nmos_4_u", [
self.netlist['n826'], self.netlist['vdd'], self.netlist['abh0']
], self),
NMOS("nmos_5_u", [
self.netlist['n826'], self.netlist['vss'], self.netlist['n318']
], self),
NMOS("nmos_6_u", [
self.netlist['n1315'], self.netlist['vss'],
self.netlist['abh0']
], self),
NMOS("nmos_7_u", [
self.netlist['abh0'], self.netlist['vss'],
self.netlist['n1062']
], self),
NMOS("nmos_8_u", [
self.netlist['n318'], self.netlist['n1062'],
self.netlist['cclk']
], self),
NMOS("nmos_9_u", [
self.netlist['n705'], self.netlist['n1062'],
self.netlist['n821']
], self),
]
vector_string = '''
PI n705
PI n821
PI cclk
PO out
001 X
010 H
001 H
101 H
110 L
101 L
001 L
010 H
'''
self.events = self.read_flex_string(vector_string)