Esempio n. 1
0
    def test_input_port_and_assigned_projection_names(self):
        T1 = pnl.TransferMechanism(name='T1')
        T2 = pnl.TransferMechanism(name='T2', input_ports=[T1])
        I1 = pnl.InputPort(owner=T2)
        I2 = pnl.InputPort(projections=[T1])
        assert I2.name == 'Deferred Init InputPort'
        T2.add_ports([I2])
        assert I1.name == 'InputPort-1'
        assert I2.name == 'InputPort-2'
        assert T2.input_ports[0].path_afferents[0].name == \
               'MappingProjection from T1[RESULT] to T2[InputPort-0]'
        assert T2.input_ports[2].path_afferents[0].name == \
               'MappingProjection from T1[RESULT] to T2[InputPort-2]'

        # ------------------------------------------------------------------------------------------------
        # TEST 10
        # Test that OutputPorts are properly named

        T1 = pnl.TransferMechanism(output_ports=['MY OUTPUT_PORT', [0]])
        assert T1.output_ports[0].name == 'MY OUTPUT_PORT'
        assert T1.output_ports[1].name == 'OutputPort-0'
        O = pnl.OutputPort(owner=T1)
        assert T1.output_ports[2].name == 'OutputPort-1'
        O2 = pnl.OutputPort()
        T1.add_ports([O2])
        assert T1.output_ports[3].name == 'OutputPort-2'
Esempio n. 2
0
 def test_output_port_variable_spec(self, mode):
     # Test specification of OutputPort's variable
     mech = pnl.ProcessingMechanism(default_variable=[[1.],[2.],[3.]],
                                    name='MyMech',
                                    output_ports=[
                                        pnl.OutputPort(name='z', variable=(pnl.OWNER_VALUE, 2)),
                                        pnl.OutputPort(name='y', variable=(pnl.OWNER_VALUE, 1)),
                                        pnl.OutputPort(name='x', variable=(pnl.OWNER_VALUE, 0)),
                                        pnl.OutputPort(name='all', variable=(pnl.OWNER_VALUE)),
                                        pnl.OutputPort(name='execution count', variable=(pnl.OWNER_EXECUTION_COUNT))
                                    ])
     expected = [[3.],[2.],[1.],[[1.],[2.],[3.]], [0]]
     for i, e in zip(mech.output_values, expected):
         assert np.array_equal(i, e)
     if mode == 'Python':
         EX = mech.execute
     elif mode == 'LLVM':
         e = pnlvm.execution.MechExecution(mech)
         EX = e.execute
     elif mode == 'PTX':
         e = pnlvm.execution.MechExecution(mech)
         EX = e.cuda_execute
     EX([[1.],[2.],[3.]])
     EX([[1.],[2.],[3.]])
     EX([[1.],[2.],[3.]])
     res = EX([[1.],[2.],[3.]])
     if mode == 'Python':
         res = mech.output_values
     expected = [[3.],[2.],[1.],[[1.],[2.],[3.]], [4]]
     for i, e in zip(res, expected):
         assert np.array_equal(i, e)
Esempio n. 3
0
 def test_output_port_variable_spec(self):
     # Test specification of OutputPort's variable
     udf = pnl.UserDefinedFunction(
         custom_function=lambda x: np.array([[1], [2], [3]]))
     mech = pnl.ProcessingMechanism(
         function=udf,
         name='MyMech',
         output_ports=[
             pnl.OutputPort(name='z', variable=(pnl.OWNER_VALUE, 2)),
             pnl.OutputPort(name='y', variable=(pnl.OWNER_VALUE, 1)),
             pnl.OutputPort(name='x', variable=(pnl.OWNER_VALUE, 0)),
             pnl.OutputPort(name='all', variable=(pnl.OWNER_VALUE)),
             pnl.OutputPort(name='execution count',
                            variable=(pnl.OWNER_EXECUTION_COUNT))
         ])
     expected = [[3.], [2.], [1.], [[1.], [2.], [3.]], [0]]
     for i, e in zip(mech.output_values, expected):
         assert np.array_equal(i, e)
     mech.execute([0])
     expected = [[3.], [2.], [1.], [[1.], [2.], [3.]], [1]]
     for i, e in zip(mech.output_values, expected):
         assert np.array_equal(i, e)
     # OutputPort mech.output_ports['all'] has a different dimensionality than the other OutputPorts;
     #    as a consequence, when added as a terminal node, the Composition can't construct an IDENTITY_MATRIX
     #    from the mech's OutputPorts to the Composition's output_CIM.
     # FIX: Remove the following line and correct assertions below once above condition is resolved
     mech.remove_ports(ports=mech.output_ports['all'])
     C = pnl.Composition(name='MyComp')
     C.add_node(node=mech)
     outs = C.run(inputs={mech: np.array([[0]])})
     assert np.array_equal(outs, np.array([[3], [2], [1], [2]]))
     outs = C.run(inputs={mech: np.array([[0]])})
     assert np.array_equal(outs, np.array([[3], [2], [1], [3]]))
Esempio n. 4
0
    def test_output_port_variable_spec_composition(self, mode):
        # Test specification of OutputPort's variable
        # OutputPort mech.output_ports['all'] has a different dimensionality than the other OutputPorts;
        #    as a consequence, when added as a terminal node, the Composition can't construct an IDENTITY_MATRIX
        #    from the mech's OutputPorts to the Composition's output_CIM.
        # FIX: Remove the following line and correct assertions below once above condition is resolved
        mech = pnl.ProcessingMechanism(default_variable=[[1.],[2.],[3.]],
                                       name='MyMech',
                                       output_ports=[
                                           pnl.OutputPort(name='z', variable=(pnl.OWNER_VALUE, 2)),
                                           pnl.OutputPort(name='y', variable=(pnl.OWNER_VALUE, 1)),
                                           pnl.OutputPort(name='x', variable=(pnl.OWNER_VALUE, 0)),
#                                           pnl.OutputPort(name='all', variable=(pnl.OWNER_VALUE)),
                                           pnl.OutputPort(name='execution count', variable=(pnl.OWNER_EXECUTION_COUNT))
                                       ])
        C = pnl.Composition(name='MyComp')
        C.add_node(node=mech)
        outs = C.run(inputs={mech: [[1.],[2.],[3.]]}, bin_execute=mode)
        assert np.array_equal(outs, [[3], [2], [1], [1]])
        outs = C.run(inputs={mech: [[1.],[2.],[3.]]}, bin_execute=mode)
        assert np.array_equal(outs, [[3], [2], [1], [2]])