def test_div(self): asm = DarwinARM64() r1 = Register('x0', False) r2 = Register('x1', False) asm.div(r1, r2) assert asm.output == 'sdiv x0, x0, x1\n'
def test_sub(self): asm = DarwinARM64() r1 = Register('x0', False) r2 = Register('x1', False) asm.sub(r1, r2) assert asm.output == 'sub x0, x0, x1\n'
def test_mul(self): asm = DarwinARM64() r1 = Register('x0', False) r2 = Register('x1', False) asm.mul(r1, r2) assert asm.output == 'mul x0, x0, x1\n'
def test_init_registesr_order(self): manager = RegisterManager(['x3', 'x3', 'x1']) assert manager.pool == [ Register('x3'), Register('x1'), ]
def test_add(self): asm = DarwinARM64() r1 = Register('x0', False) r2 = Register('x1', False) asm.add(r1, r2) assert asm.output == 'add x0, x0, x1\n'
def test_init(self): manager = RegisterManager(['x0', 'x1']) assert manager.pool == [ Register('x0'), Register('x1'), ]
def test_registers(self): class ASM(AssemblyBase): class Meta: registers = ['x0', 'x1'] asm = ASM() assert asm.registers.pool == [ Register('x0'), Register('x1'), ]
def test_str(self): register = Register('x0') assert str(register) == 'x0'
def test_init_duplicated_register(self): manager = RegisterManager(['x0', 'x0']) assert manager.pool == [Register('x0')]
def test_free_by_default(self): register = Register('x0') assert register.free is True